BICMOS output buffer circuit having overshoot protection

An output buffer circuit, comprising:

• a voltage converter having an input terminal for receiving a reference voltage having a first voltage level and a second voltage level, and an output terminal for providing an output voltage directly proportional to the reference voltage;
• a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to the output terminal of the voltage converter, and a second current electrode for providing an output signal;
• a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving an input signal, and a second current electrode coupled to a second power supply voltage terminal;
• and
• a clamping circuit coupled to the second current electrode of the first transistor for damping oscillations of the output signal and maintaining the output signal at a first predetermined voltage level corresponding to the second logic state, in response to the input signal being at a second predetermined voltage level;
• wherein the reference voltage is provided at the first voltage level as the output signal transitions from a first logic state to a second logic state, and when the output signal is at the second logic state, the reference voltage is provided at the second voltage level.

A BICMOS output buffer circuit, comprising:

• a current mirror having a first output terminal and a second output terminal;
• a first MOS transistor having a first current electrode coupled to the first output terminal of the current mirror, a control electrode for receiving a reference voltage, and a second current electrode;
• a second MOS transistor having a first current electrode and a control electrode both coupled to the second output terminal of the current mirror, and a second current electrode coupled to the second current electrode of the first MOS transistor;
• a first bipolar transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to the second output terminal of the current mirror, and a second current electrode for providing an output signal;
• a third MOS transistor having a first current electrode coupled to the second current electrode of the first bipolar transistor, a control electrode for receiving an input signal, and a second current electrode coupled to a second power supply voltage terminal;
• wherein the reference voltage is provided at a first voltage level as the output signal transitions from a first logic state to a second logic state, and when the output signal is at a second logic state, the reference voltage is provided at a second voltage level;
• and
• a clamping circuit coupled to the second current electrode of the first bipolar transistor for damping oscillations of the output signal and maintaining the output signal at a first predetermined voltage level corresponding to the second logic state, in response to the input signal being at a second predetermined voltage level.