Semi-conductor chip having interdigitated gate runners with gate bonding pads

A semiconductor device comprising

• (a) a semiconductor chip having an active area and first and second electrodes on an upper surface thereof,
• (b) a lid for covering the upper surface of the chip, the lid having upper and lower surfaces and apertures extending therethrough between said lid upper and lower surfaces,
• (c) first and second metal foils adjacent said lid lower surface, and;
• (d) at least one first bonding area wherein said first electrode is bonded to said first foil, and at least one second bonding area wherein said second electrode is bonded to said second foil, the surface area of said first bonding area not being available as an active area of said chip, said first electrode comprising:
• plural first electrode runners having first segments extending between portions of said second electrode and beneath without contacting said second foil;
• and
• each of said first electrode runners having a second segment not beneath said second foil that forms said first bonding area that has a width sufficient to bond said first foil thereto.

In a semiconductor device having a plurality of spaced semiconductor MOS devices formed in a semiconductor substrate, each of the MOS devices having a first current conduction anode, or cathode, region and a gate located on the same side of the substrate, a connector arrangement on said side of the substrate for providing separate electrical connections to said first regions and the gates comprising:

• a first plurality of elongated conductive elements formed on said side of the substrate positioned over separate groups of contacts to MOS devices, wherein each element makes electrical connections with each of the first conductive regions of its group of MOS devices, and defines a plurality of elongated contacts for making connection to the first conductive regions;
• a second plurality of elongated conductive elements on said side of the substrate and positioned over contacts to separate groups of MOS devices and separated from said first plurality of elements wherein each of the second elements makes electrical connection with each of the gates of its group of MOS devices, said second elements being substantially narrower than the first conductive elements;
• a plurality of conductive pads formed on said substrate surface at locations without MOS devices therein and separated from the first conductive elements wherein each one of the pads are connected to at least one of the second elements and wherein each of the pads defines a plurality of contacts for making connection to the gates, and
• an insulation layer extending over each of said first and second conductive elements wherein the first elements are exposed for making connections thereto.