Method of making overpass mask/insulator for local interconnects

A method for forming a gate stack, said method comprising the steps of:

• (a) providing a layer of electrically conductive material above an upper surface of a substrate;
• (b) damascening an electrically insulative layer into said layer of electrically conductive material;
• and
• (c) etching said layer of electrically conductive material and said electrically insulative layer to form the gate stack such that a portion of the layer of electrically conductive material and a portion of the electrically insulative layer comprise the gate stack and are self-aligned.

A fabrication method for forming two gate stacks of equal height but different composition above an upper surface of a substrate, said method comprising the steps of:

• (a) forming a first layer of material above the upper surface of the substrate in a first area;
• (b) forming two layers of material above the upper surface of the substrate in a second area, wherein said forming steps (a) and (b) define an interim semiconductor structure having multiple layers above the upper surface of the substrate;
• and
• (c) planarizing an upper surface of the interim semiconductor structure such that formation of a first gate stack in the first area and a second gate stack in the second area results in two gate stacks of different composition but equal height above the upper surface of the substrate.

A method for fabricating a gate stack and an overpass conductor, said method comprising the steps of:

• (a) forming the gate stack above a substrate, said gate stack forming including damascening an insulator layer into a conductor layer such that said gate stack includes a portion of said conductor layer and a portion of said insulator layer;
• (b) using said portion of said insulator layer in said gate stack as an overpass mask to partially define a conductor image for the overpass conductor;
• and
• (c) forming the overpass conductor above said gate stack such that said overpass conductor is insulated from the portion of said conductor layer in said gate stack by the portion of said insulator layer in the gate stack.