Method for manufacturing an insulating trench in a substrate for smart-power technologies

Method for manufacturing an insulation trench in an SOI substrate having integrated logic components and high-voltage power components, said method comprising the steps of:

• providing an SOI substrate having a monocrystalline silicon wafer, an insulating layer of SiO.sub.2 oriented thereon and a monocrystalline silicon layer oriented on said insulating layer;
• etching a trench into said monocrystalline silicon layer, said trench extending down to said insulating layer;
• providing sidewalls of said trench with an occupation layer containing a dopant wherein said occupation layer is produced with doped glass in a CVD method at atmospheric pressure (APCVD);
• producing diffusion regions in said monocrystalline silicon layer neighboring said trench by drive-out of dopant from said occupation layer onto said monocrystalline silicon layer wherein said drive-out, occurs during a temperature step causing said occupation layer to flow;
• removing said occupation layer completely;
• producing a silicon layer having essentially conformal edge coverage of said trench by amorphously depositing said silicon layer;
• and
• producing an insulation structure in said trench by thermal oxidation.