Process for producing storage capacitors for DRAM cells
AssigneeSiemens Aktiengesellschaft
InventorWolfgang Ro/ sner
Life of this patent
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Abstract
To produce storage capacitors for DRAM cells, dummies (81) of SiO.sub.2 which are disposed in accordance with the negative pattern of the storage node arrangement (91) are formed using auxiliary layers of SiO.sub.2 and polysilicon. The storage nodes (91) are formed, by depositing a doped polysilicon layer over the entire surface and structuring it, in such a way that they cover the area inside the dummies (81) and the side walls of the dummies (81) and that the surface of the dummies (81) is exposed in their upper region. After removing the dummies (81), a storage dielectric and a cell plate are formed. The process can be used in the production of a stacked-capacitor DRAM cell.
Claims9
A method for producing storage capacitors for DRAM cells, comprising the steps of:
- providing a substrate having a surface entirely covered by SiO.sub.2 ;
- depositing a first auxiliary layer of polysilicon over an entire surface of the SiO.sub.2 on the substrate;
- structuring the first auxiliary layer in accordance with an arrangement of the storage capacitors, so that the first auxiliary layer has openings which in each case surround storage nodes of adjacent storage capacitors;
- depositing a second auxiliary layer of SiO.sub.2 over an entire surface of the first auxiliary layer, the openings in the first auxiliary layer being filled with SiO.sub.2 ;
- back-etching the second auxiliary layer selectively with respect to the first auxiliary layer, so that the surface of the first auxiliary layer is exposed and dummy portions of SiO.sub.2 are left behind in the openings;
- completely removing the first auxiliary layer selectively with respect to SiO.sub.2 ;
- depositing surface-wide a doped polysilicon layer and structuring the doped polysilicon layer to form storage nodes such that a bottom area defined by the dummy patterns and side walls of the dummy patterns are covered with the storage nodes and the surface of the dummy patterns is in each case exposed in an upper region of the dummy patterns;
- substantially removing the dummy patterns selectively with respect to the storage nodes;
- and
- producing surface-wide a storage dielectric and producing a conductive layer as a cell plate.
Dependencies are inferred from the claim text.