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OwnerMichael D. May, Brian J. Parsons +2inventors
InventorsMichael D. May, Brian J. Parsons, Peter W. Thompson, Christopher P. H. Walker
Estimating the term…
A computer device comprises a processor for executing a plurality of concurrent processes each comprising a sequence of instructions, memory including RAM, at least one message link having input and output pins for connection to a device separate from said computer device and for transmitting message packets sequentially between the computer device and said separate device, and communication control circuitry coupled to said processor, to said memory, and to said message link. The memory provides a plurality of addressable virtual communication links. The communication control circuitry is operable: (i) in response to execution of a message instruction by said processor to address a selected one of said virtual communication links and load into the selected one information regarding the message to be effected via the virtual communication link; and (ii) to control sequential transmission through said one message link of message packets relating to a plurality of virtual communication links. A network of such computer devices and a method of operation is also described. The provision of virtual links enables several messages to be multiplexed down a single message link of the microcomputer.
A computer device comprising a processor for executing a plurality of concurrent processes each comprising a sequence of instructions, memory including RAM, at least one message link having an input and an output for connection to a device separate from said computer device and for transmitting message packets sequentially between the computer device and said separate device, said memory providing a plurality of addressable storage locations comprising a plurality of addressable virtual communication links, each virtual communication link comprising an address storage location which stores information defining a predefined destination of any message packet to be sent on that virtual communication link, and communication control circuitry coupled to said processor, to said memory, and to said message link, said communication control circuitry being effective:
A method of executing concurrent processes in a computer device having a processor, memory including RAM, communication control circuitry, and at least one message link having an input and an output connected to a device separate from the computer device for transmission of message packets between the computer device and said separate device, the method comprising the steps of:
A network comprising a plurality of computer devices, each computer device including a processor for executing a plurality of concurrent processes each comprising a sequence of instructions, memory including RAM, at least one message link having an input and an output for connection between said computer devices and for transmitting message packets sequentially between said computer devices, said memory providing a plurality of addressable storage locations comprising a plurality of addressable virtual communication links each virtual communication link comprising an address storage location which stores information defining a predefined destination of any message packet to be sent on that virtual communication link, and communication control circuitry coupled to said processor, to said memory, and to said message link, said communication control circuitry being effective:
A method of executing concurrent processes in a computer device having a processor, memory including RAM, communication control circuitry, and at least one message link having an input and an output connected to a device separate from the computer device for transmission of message packets between the computer device and said separate device, the method comprising the steps of:
Dependencies are inferred from the claim text.