US 5,495,594 AGranted

Technique for automatically adapting a peripheral integrated circuit for operation with a variety of microprocessor control signal protocols

AssigneeZilog, Inc.

InventorsCraig A. MacKenna, Monte J. Dalrymple

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Abstract

By monitoring various combinations of control signals generated by a microprocessor in a computer system in the first operational cycles after it is reset, a peripheral circuit sets itself to respond appropriately to control signals from the microprocessor according to any of several different protocols. For example, an instruction from the microprocessor to write to or read from the peripheral circuit is implemented over two control lines with one of several possible protocols. The circuit determines which protocol is being used each time the system is initialized and thereafter knows when a read or write operation is being performed. Another example is the different wait or acknowledge protocols that various microprocessors use. The peripheral circuit can thus be used with a variety of microprocessors without having to provide sets of pins dedicated to each signal protocol used by available microprocessors, and without the necessity to load a configuration register in the peripheral circuit by the microprocessor as part of the initialization process.

Claims3

Dependent claims

In a peripheral integrated circuit chip having a plurality of connection pins adapted to be connected to a microprocessor through an address and data bus and a plurality of control and status lines, a circuit that automatically responds to different microprocessor signal protocols to configure operation of drivers and receivers connected to the data bus pins, comprising:

a first storage means operably connected to receive signals from first and second connection pins for being placed into a first state by assertion of an active reset microprocessor control signal on said first pin and into a second state by assertion of an active signal of any of a bus high enable, byte/word select or upper data strobe microprocessor control signal applied to said second pin, whereby the state of the first storage means indicates whether an 8-bit or a 16-bit bus is being used by the microprocessor,
a second storage means operably connected to receive signals from said first pin and a third pin-connectable to an A0 line of the address bus for being placed into a first state by assertion of the active reset signal on said first pin and into a second state in response to activity on said third pin, whereby the state of the second storage means indicates whether the A0 address line is being used by the microprocessor,
a third storage means operably connected to receive signals from said first pin and additional fourth and fifth pins for being placed into a first state by assertion of the active reset signal on the first pin and into a second state by a simultaneous assertion of a data strobe signal on the fourth pin and a read/write control signal on the fifth pin, whereby the state of the third storage means indicates the read and write control signal protocol being used by the microprocessor, and
means responsive to the states of each of the first, second and third storage means for controlling operation of said data bus drivers and receivers.

1 more element

A peripheral integrated circuit connectable to any one of at least two types of microprocessors characterized by different control protocols including a first type that transmits a WAIT signal using a wait protocol through a first output and a read signal through a second output of said first type, a second type that transmits an ACK signal using an acknowledge protocol through a first output and a read signal through a second output of said second type, wherein said first type of microprocessor transmits a write signal through a third output of said first type and said second type of microprocessor transmits a write signal through a third output of said second type, said peripheral integrated circuit comprising:

a first input contact connectable to said first outputs of said first and second types of microprocessors, and connected to a selected one of said first and second types,
a second input contact connectable to said second outputs of said first and second types of microprocessors, and connected to said selected one of said first and second types,
a third input contact connectable to said third outputs of said first and second types of microprocessors, and connected to said selected one of said first and second types, and
a logic circuit connected to said first, second and third input contacts, wherein said logic circuit generates at least one internal control signal having a logic state indicative of whether said selected one is said first or second type of microprocessor, said logic circuit including
an OR gate having a first input responsive to a signal received at said second input contact, a second input responsive to a signal received at said third input contact, and an output, and
a flip-flop having a data input connected to said output of said OR gate, a clock input connected to said first input contact, and an output providing said at least one internal control signal having said logic state indicative of whether said selected one is said first or second type of microprocessor.

3 more elements

Dependencies are inferred from the claim text.