US 5,495,588 AGranted

Programmable controller having joined relay language processor and general purpose processor

AssigneeAllen-Bradley Company, Inc.

InventorsAnthony G. Gibart, Kurt Knull

Life of this patent

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Abstract

A programmable controller for executing general instructions and relay ladder instructions employs a general purpose microprocessor together with a high speed relay ladder processor. The relay ladder instruction in a user program are executed by the special processor exclusively. When a general instruction is encountered, the special processor releases the general purpose microprocessor from a wait state and provides it with data in response to a previous long read instruction. This data is interpreted by the microprocessor to indicate the next instruction to be executed and points to a series of machine instructions terminating in another long read instruction to a designated address. When a read of this designated address is detected by the special processor, thus indicating the conclusion of the execution of the general instruction, the special processor puts the microprocessor back in the wait state and continues to execute relay ladder instructions in the user program if any. The allocation technique may be used with a large class of general purpose microprocessors with no modification and without the need for separate allocation circuitry.

Claims8

Dependent claims

A programmable controller for executing a user program having relay ladder instructions and general instructions comprising:

a computer memory storing the user program, the memory holding words at addresses in an address space including at least one predetermined designated address;
A. a general purpose microprocessor:
(a) providing the computer memory with first addresses via an address bus and receiving words from the computer memory via a data bus,
(b) responding to the cessation of a wait signal by sequentially executing general instructions as routines of at least one micro-instruction designated by an instruction address in a microprocessor instruction pointer,
(c) responding to at least one micro-instruction to cause the microprocessor instruction pointer to obtain its instruction address from the predetermined designated address of the memory;
(d) responding to the initiation of the wait signal by suspending the sequential execution of general instructions,
B. a special processor:
(i) monitoring the first addresses of the general processor;
(ii) initiating the wait signal upon detecting the predetermined designated address on the address bus;
(iii) providing the computer memory with second addresses via the address bus and receiving words from the computer memory via the data bus,
(iv) receiving instructions from the user program in the computer memory at addresses identified by an instruction address in a processor instruction pointer,
(v) executing the instructions only if they are relay ladder instructions,
(vi) if an instruction is not a relay ladder instruction, ceasing the wait signal and providing the microprocessor with a word on the data bus so that the word is received by the microprocessor instruction pointer as its instruction address for the microprocessor to begin execution of the instruction that is not the relay ladder instruction.

10 more elements

A method of executing a user program, having relay ladder instructions and general instructions, in a programmable controller having:

a computer memory storing the user program, the memory having a plurality of words at addresses in an address space including at least one predetermined designated address, a general purpose microprocessor executing the general instructions and detecting and servicing the interrupts and having address lines for identifying addresses of the computer memory to be read by the microprocessor, a special purpose processor executing the relay ladder instructions and detecting interrupts, the method comprising the steps of:
(a) executing a general instruction with the microprocessor as a sequence of at least one micro-instruction the sequence terminating, upon the occurrence of a relay ladder instruction, in a micro-instruction that causes the microprocessor to read the predetermined designated address and obtain its next instruction at an address read from the predetermined address;
(b) monitoring the address lines of the microprocessor with the special purpose processor to detect an attempted reading of the predetermined designated address by the microprocessor;
(c) putting the microprocessor into a wait state, prior to the microprocessor obtaining the next address, upon the attempted reading of step (b);
(d) executing the relay ladder instructions with the special processor until a general instruction is received;
(e) releasing the microprocessor from the wait state upon receipt of the general instruction and providing the address of the first micro-instruction of a sequence of at least one micro-instruction performing no operation, the sequence terminating in a micro-instruction that causes the microprocessor to read the contents of the predetermined designated address of the memory and jump to an address indicated by the words of the predetermined designated address, in response to the attempted reading of step (b).

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/365,979Filed 28 Dec 1994 · continuation
Priority: 18 Nov 1993
Granted: 27 Feb 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/3877
Concurrent instruction execution, e.g. pipeline or look ahead: using a secondary processor, e.g. coprocessor
G05B 19/052
Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts: linking several…
G06F 9/3879
Using a secondary processor, e.g. coprocessor: for non-native instruction execution, e.g. executing a command; for Java instruction set
G05B 2219/15127
Plc structure of the system: bit and word, byte oriented instructions, boolean and arithmetic operations