Programmable timing logic system for dual bus interface
AssigneeUnisys Corporation
InventorsWayne C. Datwyler, Paul B. Ricci
Life of this patent
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Abstract
A programmable timing logic system for enabling access to a first or second bus, of dual system busses, by a central processor and/or a protocol-timing translation logic unit wherein messages may be received from one bus while command/control data is being transmitted to the other bus. Incomplete command cycles are retried a specific number "n" of times, each for a preset predetermined time period of "p" microseconds.
Claims13
In a network where a first resource means and a second resource means are connected via a dual channel bus interface means for communication with first and second system busses via first and second bus interface unit channels, a system for establishing time periods for command and data transfers between said first and second resource means and said first and second system busses, said system comprising:
- (a) means for requesting access to said first or second system busses for a preset predetermined "p" period of time wherein "p" represents a preset period of time in microseconds that the access request will be operable on a bus before said access request will no longer be accepted by said bus;
- (b) means for granting system bus access to commands from said first resources means and to messages from said second resource means when said first or second bus is not busy during said "p" period of time;
- (c) timing means for generating said predetermined preset time periods "p" during which requests for system bus access are operable;
- (d) and wherein said dual channel bus interface means can operate simultaneously for transmission on one bus and reception on the other bus of said first and second system busses.
A programmable logic timing system for dual communication channels between first and second resource means and first and second system busses, said logic timing system comprising:
- (a) first means for regulating access requests of said system busses to said first and second resource means when said first and second resource means seek to transmit to said system busses;
- (b) second means for regulating access requests of said first and second resource means to receive data from said system busses when said first and/or second resource means are not busy;
- (c) timing means for setting a timing period that said first and second regulating means is permitted to initiate access, said timing period being limited to p.times.n wherein p is a preset time period in microseconds allowed for each single access request and "n" is a preset number of retry times that said access to said first and second resource means or access to said first and second system bus is preset for operability, said timing means including:
- (i) means to preset said value of "n" to limit the number of cycles that an access request can be re-tried;
- (ii) means for setting said preset time period "p" to limit the time period for each single access request.
Dependencies are inferred from the claim text.