Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count

A central processing unit comprising:

• A) first and second basic processing units adapted to redundantly perform data manipulations on received data to obtain first and second data manipulation results;
• B) a cache unit for receiving data manipulation results from said first and second basic processing units, said cache unit including means for storing such data manipulation results as information words among an array of information words and for transferring specified information words simultaneously to both said first and second basic processing units upon a request therefrom;
• C) first cache interface control signal generation means in said first basic processing unit and second cache interface control signal generation means in said second basic processing unit, each said first and second cache interface control signal generation means issuing first and second groups of control signals, said groups of control signals being nominally identical, and said second groups of control signals being nominally identical;
• D) a first control signal bus for communicating said first group of control signals from said first basic processing unit to said cache unit;
• E) a second control signal bus for communicating said second group of control signals from said second basic processing unit to said cache unit;
• F) control circuitry means in said cache unit for receiving said first and second groups of control signals and for employing such control signals to control operations in said cache unit instituted by said first and second basic processing units;
• G) first parity generating means in said first basic processing unit for developing group one parity information comprising at least one parity bit for said first group of control signals generated therein;
• H) second parity generating means in said first basic processing unit for developing group two parity information comprising at least one parity bit for said second group of control signals generated therein;
• I) third parity generating means in said second basic processing unit for developing parity information comprising at least one parity bit for said first group of control signals generated therein;
• J) fourth parity generating means in said second basic processing unit for developing parity information comprising at least one parity bit for said second group of control signals generated therein;
• K) a first parity bus for communicating said group two parity information developed in said first basic processing unit to said second basic processing unit;
• L) a second parity bus for communicating said group one parity information developed in said second basic processing unit to said first basic processing unit;
• M) parity checking means in said first basic processing unit for comparing said group one parity information developed in said first basic processing unit to said group one parity information developed in said second basic processing unit and for issuing an error signal in response to a miscompare;
• and
• N) parity checking means in said second basic processing unit for comparing said group two parity information developed in said first basic processing unit to said group two parity information developed in said second basic processing unit and for issuing an error signal in response to a miscompare;
• and
• O) control means responsive to a control signal group parity error sensed in at least one of said first basic processing unit and said second basic processing unit to take predetermined remedial action.