US 5,495,573 AGranted

Error logging system with clock rate translation

AssigneeUnisys Corporation

InventorsWayne C. Datwyler, Long V. Ha, Dan T. Tran

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Abstract

An error logging system where errors are captured on dual system busses operating at a lower clock rate (16 MHz) than the processor which receives the error information. The system functions to substantially reduce the loads on the processor in addition to maximizing the use of the system bus drivers which are pin-constrained. The processor operates at a higher clock rate (32 MHz). Processor commands to read error data from an error log register are synchronized down to the 16 MHz rate, then enabled onto a processor bus after a second synchronization operation back to the higher (32 MHz) rate. Provision is made for identifying several different types of error categories. An expandable error log register system is provided which uses selected bit positions to identify types of errors logged to the processor which also enables expansitivity for adding in future types of errors into the error logging system and renders compatibility for a processor operating at first clock rate with error data sensed at a second clock rate.

An error logging system for a computer network wherein dual system busses carrying digital data are monitored by a system bus interface logic unit at a Y clock rate and enabled to report to a central processor means at an X clock rate, said system comprising:

(a) said system bus logic unit for monitoring data on said dual system busses to detect multiple types of errors, including:
(a1) first error logging register means receiving error data at said Y clock rate, from error sensing means;
(a2) said error sensing means for monitoring data on said dual system busses and generating separate error data signals for
(i) an error code for invalid address;
(ii) an error code for expiration of retry transmission time;
(iii) an error code for invalid data error;
(b) means to signal said processor means that said error data signals have accumulated in said first error logging register means;
(c) said processor means for generating a Read command at said X clock rate to a data path control logic unit;
(d) said data path control logic unit for converting said X clock rate Read command to a Y clock rate Read command for transmittal to said first error logging register means and including:
(d1) means for shifting at said Y clock rate said separate error data signals from said first error logging register means to a second error logging register means in a data path gate array means;
(d2) means to parallel load a synchronization register means, at said X clock rate, with said separate error data signals from said second error logging register means;
(e) data path gate array means for receiving said separate error data signals at said Y clock rate in said second error logging register means and including:
(e1) parallel transfer means, controlled by said data path control logic, for loading said separate error data signals from said second error logging register means into said synchronization register means at said X clock rate said parallel transfer means including:
(e1a) processor bus means for transmitting said separate error data signals to said processor means.

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Abstract

Claims5