Mirrored memory multi-processor system

A multiprocessor, shared memory system comprising at least two processors, each processor having:

• (a) a memory unit having at least three ports;
• (b) a processor and memory management unit coupled to the memory unit through a first port;
• (c) at least first and second internal interprocessor interfaces, each coupled to the processor and memory management unit, and directly to respective second and third ports of the memory unit;
• (d) at least first and second external interprocessor interfaces, each coupled to a respective one of the at least first and second internal interprocessor interfaces, to the respective second and third ports of the memory unit, and to a corresponding external interprocessor interface of at least one other processor;
• the external and internal interprocessor interfaces controlling data accesses to the memory unit by at least one other processor, and controlling data accesses by the processor and memory management unit to the memory unit of at least one other processor, whereby each processor is normally active and may, in a single operation, independently access only its memory unit, only the memory unit of at least one other processor, or both its memory unit and the memory unit of at least one other processor.

A multiprocessor, shared memory system comprising paired processors, each processor having:

• (a) a memory bus;
• (b) a memory unit coupled to the memory bus;
• (c) a processor bus;
• (d) a processor and memory management unit coupled to the processor bus;
• (e) a memory-processor interface coupled to the memory bus and the processor bus, for controlling transfers of data between the memory unit and the processor and memory management unit;
• (f) first and second external interprocessor interfaces each coupled to respective first and second internal interprocessor busses and to respective first and second external interprocessor busses, the first and second external interprocessor busses directly coupling each processor to the corresponding first and second external interprocessor busses of its paired processor, the first and second external interprocessor bus interfaces for controlling information transfers between the respective first and second external interprocessor busses and the respective first and second internal interprocessor busses;
• (g) first and second internal interprocessor interfaces, each respectively coupled to the first and second internal interprocessor busses and to the processor bus, for controlling information transfers between the respective first and second internal interprocessor busses and the processor bus;
• (h) first and second interprocessor-memory bus interfaces each respectively coupled to the first and second internal interprocessor busses and to the memory bus for controlling information transfers between the respective first and second internal interprocessor busses and the memory bus;
• and
• (i) data comparison means coupled to receive data from the memory unit of the processor and from the corresponding memory of its paired processor, for comparing the data accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of its paired processor, and signaling an error condition if the data accessed from the paired processors are not equivalent;
• whereby each processor is normally active and may, in a single operation, independently access only its memory unit, only the memory unit of its paired processor, or both its memory unit and the memory unit of its paired processor.

A method for equalizing the data contents of the memory units of a multiprocessor, shared memory system comprising at least two processors, each processor having at least two external communications paths, a memory unit having at least three ports, a processor and memory management unit coupled to the memory unit through a first port, first coupling means for independently coupling at least two ports of the memory unit to at least two of the external communications paths of another processor, second coupling means for independently coupling the processor and memory management unit to at least two of the external communications paths of another processor, data comparison means, coupled to receive at least the data values from the memory unit of the processor and from the corresponding memory of at least one other processor, for comparing data values accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of at least one other processor, the method comprising the steps of:

• (a) operating one processor in an out-of-service mode, whereby the out-of-service processor is enabled to access the memory unit of a second processor;
• (b) operating the second processor in an in-service non-duplex mode, whereby the in-service processor is disabled from accessing the memory unit of the out-of-service processor but operates to execute at least one operational task;
• (c) copying selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor;
• (d) after all selected data is copied, switching the in-service processor to a duplex mode, whereby the in-service processor is enabled to access the memory unit of the out-of-service processor while operating to execute at least one operational task;
• (e) re-copying a portion of the selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor;
• (f) comparing the re-copied portion of data in the memory unit of the in-service processor with the corresponding portion of the previously copied data from the memory unit of the in-service processor, and indicating an error if the compared data is not equivalent;
• (g) writing data changed by the execution in the in-service processor of at least one operational task to the memory unit of the out-of-service processor;
• (h) repeating steps (e) through (g) until all of the selected data is re-copied into the memory unit of the out-of-service processor;
• (i) thereafter, operating the out-of-service processor in an in-service mode.

A method for equalizing the data contents of the memory units of a multiprocessor, shared memory system comprising at least two processors, each processor having at least two external communications paths, a memory unit having at least three ports, a processor and memory management unit coupled to the memory unit through a first port, first coupling means for independently coupling at least two ports of the memory unit to at least two of the external communications paths of another processor, second coupling means for independently coupling the processor and memory management unit to at least two of the external communications paths of another processor, the first coupling means controlling data accesses to the memory unit by at least one other processor, and the second coupling means controlling data accesses by the processor and memory management unit to the memory unit of at least one other processor, data comparison means, coupled to receive at least the data values from the memory unit of the processor and from the corresponding memory of at least one other processor, for comparing data values accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of at least one other processor, and signaling an error condition if the accessed data values are not equivalent, whereby each processor may independently access only its memory, only the memory of at least one other processor, or both its memory and the memory of at least one other processor, the method comprising the steps of:

• (a) operating one processor in an out-of-service mode, whereby the out-of-service processor is enabled to access the memory unit of a second processor;
• (b) operating the second processor in an in-service non-duplex mode, whereby the in-service processor is disabled from accessing the memory unit of the out-of-service processor but operates to execute at least one operational task;
• (c) copying selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor;
• (d) after all selected data is copied, switching the in-service processor to a duplex mode, whereby the in-service processor is enabled to access the memory unit of the out-of-service processor while operating to execute at least one operational task;
• (e) re-copying a portion of the selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor;
• (f) comparing the re-copied portion of data in the memory unit of the in-service processor with the corresponding portion of the previously copied data from the memory unit of the in-service processor, and indicating an error if the compared data is not equivalent;
• (g) writing data changed by the execution in the in-service processor of at least one operational task to the memory unit of the out-of-service processor;
• (h) repeating steps (e) through (g) until all of the selected data is re-copied into the memory unit of the out-of-service processor;
• (i) thereafter, operating the out-of-service processor in an in-service mode.

A multiprocessor shared memory system comprising two processors, each of the two processors having:

• an associated memory including first, second, and third ports;
• a processing unit coupled for access to the associated memory through the second of the three ports, the processing unit independently accessing its associated memory through the second port thereof;
• and
• coupling means for redundantly and directly coupling the processing unit to the memory associated with the processing unit of the other of the two processors through the first and third ports of the memory of the other processing unit, the processing unit at the same time capable of accessing the memory associated with the processing unit through the second port and of accessing the memory associated with the other processing unit through the first and third ports of the memory of the other processing unit.