Circuit for ensuring that a local interrupt controller in a microprocessor is powered up active

A computer system, comprising:

• a microprocessor having a local interrupt controller, said microprocessor being responsive to a first reset signal and being connected to a first interrupt control signal and a second interrupt control signal, wherein said microprocessor asserts said first interrupt control signal when said first reset signal is asserted;
• means for providing a second reset signal, said second reset signal being asserted during a power up sequence, and said second reset signal being deasserted a predetermined amount of time after it has been asserted;
• an external interrupt controller connected to said first and second interrupt control signals, said external interrupt controller further being responsive to said second reset signal, wherein said external interrupt controller samples the state of said first interrupt control signal after said second reset signal is deasserted, said external interrupt controller periodically pulsing said second interrupt control signal asserted for a first predetermined period if said first interrupt control signal is sampled asserted, and wherein if said microprocessor samples said second interrupt control signal asserted when said first reset signal is deasserted, said local interrupt controller is deactivated;
• and
• a circuit for ensuring that said local interrupt controller is powered up active, said circuit including:
• means responsive to said second reset signal for providing said first reset signal, said first reset signal being asserted shortly after said second reset signal is asserted, and said first reset signal being maintained asserted while said second reset signal is asserted;
• means responsive to said second reset signal for sampling the state of said second interrupt control signal after said second reset signal has been deasserted;
• and
• means coupled to said sampling means and to said first reset signal providing means for waiting a second predetermined period after said second interrupt control signal has been sampled asserted, wherein said second predetermined period is greater than the first predetermined period, and wherein said first signal providing means deasserts said first reset signal shortly after said second predetermined period.

A method of ensuring that a local interrupt controller in a microprocessor is powered up active, the microprocessor being responsive to a first reset signal and being connected to a first interrupt control signal and a second interrupt control signal, wherein an external interrupt controller is connected to the first and second interrupt control signals, the external interrupt controller further being responsive to a second reset signal, the second reset signal being asserted during a power up sequence, the second reset signal being deasserted a predetermined amount of time after it has been asserted, wherein the microprocessor asserts the first interrupt control signal when the first reset signal is asserted, wherein the external interrupt controller samples the state of the first interrupt control signal after the second reset signal is deasserted, the external interrupt controller periodically pulsing the second interrupt control signal asserted for a first predetermined period if the first interrupt control signal is sampled asserted, and wherein if the microprocessor samples the second interrupt control signal asserted when the first reset signal is deasserted, the local interrupt controller is deactivated, the method comprising the steps of:

• asserting the first reset signal shortly after the second reset signal is asserted;
• maintaining the first reset signal asserted while the second reset signal is asserted;
• sampling the state of the second interrupt control signal after the second reset signal has been deasserted;
• waiting a second predetermined period after said second interrupt control signal has been sampled asserted, wherein said second predetermined period is greater than the first predetermined period;
• and
• deasserting the first reset signal said second predetermined period shortly after said second interrupt control signal is sampled asserted.