Testing buffer/register

An integrated circuit operable in test and normal modes, comprising:

• input circuitry for receiving input data;
• output circuitry for transmitting output data;
• application logic circuitry coupled to said input circuitry and said output circuitry for performing a function on said input data and producing said output data;
• input test cells coupled to said input circuitry, for performing internally controlled test operations while said integrated circuit is in said test mode;
• output test cells coupled to said output circuitry, for performing internally controlled test operations while said integrated circuit is in said test mode;
• and
• test control circuitry coupled to said input and output test cells to communicate serial data to and from said integrated circuit, said serial data communicated to said test cells by said test control circuitry to setup said input and output test cells for a selected internally controlled test operation while said integrated circuit is in said normal node, said test control circuitry having control outputs that are coupled to said input and output test cells and which control execution of said internally controlled test operation by said input and output test cells after said setup is complete, said test control circuitry communicating serial data from said integrated circuit by serially unloading test results from said input and output test cells after said internally controlled test operation has completed and said integrated circuit returns to said normal mode.