US 5,495,478 A · Apparatus and method for processing asynchronous transfer mode cells

Abstract

Egress processing of asynchronous transfer mode (ATM) cells is performed by an egress processor (18) that receives ATM cells from an ingress processor (16) through a cell bus (20). ATM cells are received in the egress processor (18) through an egress FIFO buffer (32) and placed within available space in an ECELL memory (38) through a single cell FIFO buffer (34) as controlled by a cell loader (36). A linker (44) chains together ATM cells, no matter where they are located in the ECELL memory (38), corresponding to a particular call into a specific packet by placing pointer information within each ATM cell of a specific packet such that each ATM cell points to the next ATM cell within the packet. The linker (44) places the cell location of the first cell of the packet into a packet FIFO buffer (52) of a cell location buffer (48). An unlinker (46) uses the cell location within the packet FIFO buffer (52) to transmit ATM cells from the ECELL memory (38) to an egress line interface (22) according to the pointer information placed by the linker (44) into each ATM cell. When the unlinker (46) is ready to transmit ATM cells from the ECELL memory (38) before the linker (44) has finished chaining together a packet, the linker (44) places the cell location information directly into a cell FIFO buffer (50) within the cell location buffer (48) instead of within each ATM cell for immediate use by the unlinker (46).

Claims20

Dependent claims

An apparatus for processing asynchronous transfer mode cells, comprising:

a memory for receiving and storing a plurality of asynchronous transfer mode cells, said asynchronous transfer mode cells defining a plurality of packets;
a linker coupled to said memory for placing pointer information within each asynchronous transfer mode cell stored in said memory in order to chain together corresponding asynchronous transfer mode cells into associated specific packets;
an unlinker coupled to said memory for transmitting from said memory asynchronous transfer mode cells corresponding to a specific packet as chained together by said linker.

An apparatus for processing asynchronous transfer mode cells, comprising:

a memory for receiving and storing a plurality of asynchronous transfer mode cells corresponding to a plurality of packets, wherein each packet represents a separate call;
a cell loader for controlling storage of asynchronous transfer mode cells into said memory and for identifying virtual circuit identifier information contained within each asynchronous transfer mode cell;
a linker for placing pointer information within each asynchronous transfer mode cell stored within said memory, said linker identifying specific packets by chaining together corresponding asynchronous transfer mode cells regardless of where asynchronous transfer mode cells are stored within said memory;
an unlinker for outputting asynchronous transfer mode cells corresponding to a specific packet as chained together by said linker;
a virtual circuit identifier state table accessible by said linker and said unlinker for storing information corresponding to each specific packet, said virtual circuit identifier state table having entries accessed by said virtual circuit identifier information within each asynchronous transfer mode cell, wherein said virtual circuit identifier state table controls processing of said asynchronous transfer mode cells by said linker.

2 more elements

Dependencies are inferred from the claim text.

Apparatus and method for processing asynchronous transfer mode cells

Life of this patent

Apparatus and method for processing asynchronous transfer mode cells

Life of this patent

Abstract

Claims20