Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory cell array blocks each having at least one word line and at least one pair of bit lines and associated with a word line drive circuit, a precharge circuit and a sense amplifier circuit;
• a block select circuit for selectively outputting a block select signal corresponding to one of said memory cell array blocks;
• an address latch circuit associated with said word line drive circuit and a refresh counter;
• and
• an address buffer for outputting word address signals to said memory cell array blocks,
• wherein said word line drive circuit associated with said address latch circuit which latches and continuously outputs one of said word address signal thereto according to a first logical level of said block select signal and said word line driver circuit continuously activates said word line according to an output signal of said address latch circuit.

A semiconductor device comprising:

• a plurality of memory cell blocks each including a plurality of word lines, a plurality of bit lines and a plurality of memory cells each provided at one of intersections of said word lines and said bit lines;
• a plurality of block selection signals provided correspondingly to said memory cell blocks;
• a control circuit block responding to a part of address information to change one of said plurality of block selection signals to an active level;
• a plurality of latch circuits, each provided for an associated one of said memory cell blocks, which latch a remaining portion of said address information in response to said active level of an associated one of said block selection signals;
• and
• a plurality of word drivers, each provided for an associated one of said memory cell blocks, for selecting one of said word lines in response to a content of an associated one of said latch circuits and driving said one of said word lines to a selection level, said one of said word lines being maintained to said selection level until the content of said associated one of said latch circuits is changed.