Low power voltage detector circuit including a flash memory cell

A nonvolatile memory device comprising:

• a conductor for coupling to receive an input voltage;
• a memory cell array comprising a plurality of nonvolatile memory cells arranged in a matrix of rows and columns, wherein the memory cell array is coupled to receive the input voltage;
• a voltage detector circuit coupled to the conductor for detecting whether the input voltage exceeds a trip-point voltage, the voltage detector circuit comprising:
• a nonvolatile memory cell including a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate, wherein the nonvolatile memory cell has a programmable threshold voltage and the threshold voltage is programmed such that the nonvolatile memory cell is switched on to set the first node to system ground if the input voltage exceeds the trip-point voltage;
• a first transistor including a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to the input voltage, the control electrode for coupling the first terminal to the second terminal in response to the biasing voltage;
• an inverter having an input coupled to the first node and an output for indicating whether the input voltage exceeds the trip-point voltage;
• and
• a control circuit coupled to the output of the inverter and the control electrode of the first transistor, the control circuit for supplying the output of the inverter to the control electrode of the first transistor as the biasing voltage when power is first applied to the nonvolatile memory device such that the first transistor is switched off when the output of the inverter indicates that the input voltage exceeds the trip-point voltage, and for supplying the biasing voltage to the control electrode of the first transistor when erase and program operations are performed on the memory cell array such that the first transistor is switched on continuously.

A nonvolatile memory device comprising:

• a conductor for coupling to receive an input voltage;
• a memory cell array comprising a plurality of nonvolatile memory cells arranged in a matrix of rows and columns, wherein the memory cell array is coupled to receive the input voltage;
• a voltage detector circuit coupled to the conductor for detecting whether the input voltage exceeds a trip-point voltage, the voltage detector circuit comprising:
• a nonvolatile memory cell including a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate, wherein the nonvolatile memory cell has a programmable threshold voltage and the threshold voltage is programmed such that the nonvolatile memory cell is switched on to set the first node to system ground if the input voltage exceeds the trip-point voltage;
• an inverter having an input coupled to the first node and an output, the inverter for indicating that the input voltage is less than the trip-point voltage by setting the output to system ground and for indicating that the input voltage is at least the trip-point voltage by setting the output to the input voltage;
• and
• a first transistor including a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to the input voltage, the control electrode for coupling the first terminal to the second terminal in response to the biasing voltage, wherein the first transistor sets the first node to the input voltage if the input voltage is less than the trip-point voltage.

A nonvolatile memory device comprising:

• a conductor for coupling to receive an input voltage;
• a memory cell array comprising a plurality of nonvolatile memory cells arranged in a matrix of rows and columns, wherein the memory cell array is coupled to receive the input voltage;
• a voltage detector circuit coupled to the conductor for detecting whether the input voltage exceeds a trip-point voltage, the voltage detector circuit comprising:
• a nonvolatile memory cell including a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate, wherein the nonvolatile memory cell has a programmable threshold voltage and the threshold voltage is programmed such that the nonvolatile memory cell is switched on to set the first node to system ground if the input voltage exceeds the trip-point voltage;
• a first transistor including a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to the input voltage, the control electrode for coupling the first terminal to the second terminal in response to the biasing voltage, wherein the first transistor is switched on continuously for setting the first node to the input voltage if the input voltage is less than the trip-point voltage;
• and
• an inverter having an input coupled to the first node and an output for indicating whether the input voltage exceeds the trip-point voltage.

A method for indicating whether an input voltage exceeds a trip-point voltage:

• applying the input voltage to a gate of a nonvolatile memory cell having a threshold voltage programmed to be the trip-point voltage, wherein the nonvolatile memory cell includes a drain coupled to a first node and a source coupled to system ground;
• p1 detecting that a voltage of the first node is set to a supply voltage if the nonvolatile memory cell is switched off in response to the input voltage being less than the trip-point voltage;
• indicating that the input voltage is less than the trip-point voltage if the voltage of the first node is set to the supply voltage;
• detecting that a voltage of the first node is set to system ground if the nonvolatile memory cell is switched on in response to the input voltage exceeding the trip-point voltage;
• and
• indicating that the input voltage exceeds the trip-point voltage if the voltage of the first node is set to system ground.