Circuit for controlling a self-refresh period in a semiconductor memory device

A period control circuit for self-refresh operation in a semiconductor memory device comprising:

• pulse generating means for outputting a predetermined periodic pulse train in response to an external control signal;
• frequency-dividing means for outputting a plurality of pulse trains which have different periods from each other by frequency-dividing said pulse train output from said pulse generating means;
• at least one temperature detecting means for detecting an ambient temperature of said memory device and for outputting a temperature detection signal when said ambient temperature reaches a predetermined level;
• at least one voltage detecting means for detecting a power supply voltage applied to said memory device and for outputting a voltage detection signal when said power supply voltage reaches a predetermined level;
• combination pulse train generating means for outputting a plurality of combination pulse trains by combining said pulse trains output from said frequency-dividing means;
• and
• pulse selecting means for outputting a self-refresh master clock by selecting one of said combination pulse trains in response to said voltage detection signal and said temperature detection signal.

A circuit for controlling a self-refresh period of a semiconductor memory device, comprising:

• a pulse generating circuit which outputs a periodic pulse train in response to an external control signal;
• a frequency-dividing circuit which outputs a plurality of pulse trains having different periods from each other by frequency-dividing said periodic pulse train output by said pulse generating circuit;
• a temperature detection circuit which detects an ambient temperature of said memory device and outputs a temperature detection signal when said ambient temperature reaches a predetermined temperature level;
• a voltage detection circuit which detects a power supply voltage applied to said memory device and outputs a voltage detection signal when said power supply voltage reaches a predetermined voltage level;
• and,
• a pulse selection circuit which outputs a self-refresh master clock by selecting one of said pulse trains in response to said temperature detection signal and said voltage detection signal.

A circuit for controlling a self-refresh period of a semiconductor memory device, comprising:

• a pulse generating circuit which outputs a periodic pulse train in response to an external control signal;
• a frequency-dividing circuit which outputs a plurality of pulse trains having different periods from each other by frequency-dividing said periodic pulse train output by said pulse generating circuit;
• a temperature detection circuit which detects an ambient temperature of said memory device and outputs a temperature detection signal when said ambient temperature reaches a predetermined temperature level;
• a voltage detection circuit which detects a power supply voltage applied to said memory device and outputs a voltage detection signal when said power supply voltage reaches a predetermined voltage level;
• a combination pulse train generating circuit which outputs a plurality of combination pulse trains by variously combining said pulse trains output by said frequency-dividing means;
• a pulse selection circuit which outputs a self-refresh master clock by selecting one of said combination pulse trains in response to said temperature detection signal and said voltage detection signal.