Memory testing through cumulative word line activation
AssigneeU.S. Philips Corporation
InventorManoj Sachdev
Life of this patent
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Abstract
An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises I.sub.DDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for I.sub.DDQ test purposes only.
Claims6
An electronic circuit having a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines, characterized, in that the circuit comprises test means operative to render the plurality of word lines active in parallel by sequentially and cumulatively increasing a number of active word lines among the plurality of word lines.
A method of testing a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines, characterized, in that the method comprises:
- rendering the plurality of word lines active by sequentially cumulatively and increasing a number of active word lines among the plurality of word lines;
- enabling writing a particular logic state in the memory cells connected to the word lines last made active;
- monitoring a quiescent current when the plurality of word lines are active in parallel.
Dependencies are inferred from the claim text.