Pre-charged exclusionary wired-connected programmed redundant select

A redundant decode structure of a high speed clocked memory device, comprising:

• a plurality of programmable elements of an exclusionary wired-connection redundant select circuit;
• a plurality of address input signals which are connected to and control the plurality of programmable elements;
• a first controlling clock input signal, provided to the plurality of programmable elements, characterized as having an active portion and an inactive portion;
• an enable circuit connected to the plurality of programmable elements which enables or disables the exclusionary wired-connection redundant select circuit;
• means, connected to the plurality of programmable elements, for programming an address of a defective element of the high speed clocked memory device by disconnecting all the programmable elements of the plurality of programmable elements of the exclusionary wired-connection redundant select circuit which are not representative of the address of the defective element from their corresponding address input signals of the plurality of address input signals, wherein, after programming the address of the defective element, during the inactive portion of the first controlling clock the address of the defective element becomes valid;
• an output signal of the exclusionary wired-connection redundant select circuit connected to the means for programming an address of a defective element of the high speed clocked memory device;
• and
• means for storing the output signal of the exclusionary wired-connection redundant select circuit.

A method for replacing defective elements of a high speed clocked memory device, comprising the steps of:

• enabling an exclusionary wired-connection redundant select circuit, wherein the exclusionary wired-connection redundant select circuit has a plurality of address input signals which are connected to and control a plurality of programmable elements;
• a first controlling clock input signal, provided to the plurality of programmable elements, characterized as having an active portion and an inactive portion;
• an enable circuit connected to the plurality of programmable elements which performs the step of enabling the exclusionary wired-connection redundant select circuit;
• programming an address of a defective element of the high speed clocked memory device by disconnecting all the programmable elements of the plurality of programmable elements of the exclusionary wired-connection redundant select circuit which are not representative of the address of the defective element from their corresponding address input signals of the plurality of address input signals;
• and
• enabling a redundant element having the same address as the address of the defective element;
• and
• wherein after the step of programming the address of the defective element, during the inactive portion of the first controlling clock the address of the defective element becomes valid.