Redundancy scheme for memory circuits

A memory circuit comprising:

• a plurality of main memory elements each located at an intersection of a column and a row;
• address decoders having inputs for receipt of address input information, the address decoder for selecting a main memory element by asserting a decode line in response to the address input;
• redundant memory elements;
• programmable redundant decoders coupled to the redundant memory elements for selecting one of the redundant memory elements by asserting a redundant decode line in response to a predetermined address input information;
• select circuit coupling a selected one of said plurality of main memory elements and a corresponding one of said redundant memory elements to a data line in response to a corresponding decode line and redundant decode line;
• sensing circuit having an input coupled to the data line for detecting contents of an accessed memory element;
• and
• means coupled to the data line for generating on the data line a redundant signal that is stronger than a defective signal when a redundant element is selected,
• wherein the stronger redundant signal overrides the defective signal, eliminating the need for disabling the defective element.

In a dynamic random access memory circuit, a column redundancy circuit comprising:

• a column select transistor for coupling a main column line to a first segment of a data line;
• a resistive element coupling the first segment of the data line to a second segment of the data line;
• a data sense amplifier coupled to the second segment of the data line;
• and
• a redundant column select transistor for coupling a redundant column line to the second segment of the data line,
• wherein, a voltage drop across the resistive element causes data from the redundant column line to override data from the main column line when a redundant column is selected.

In a static random access memory circuit, a row redundancy circuit comprising:

• a main memory cell including a storage latch and a pair of access transistors coupling the storage latch to a first segment of a complementary pair of bit lines, respectively;
• a resistive element coupling the first segment of the complementary pair of bit lines to a second segment of the complementary pair of bit lines;
• a redundant memory cell including a redundant storage latch and a redundant pair of access transistors coupling the redundant storage latch to the second segment of the complementary pair of bit lines, respectively;
• and
• a sense circuit having an input coupled to the second segment of the complementary pair of bit lines,
• wherein, a voltage drop across the resistive element causes the contents of the redundant memory cell to override the contents of the main memory cell when the redundant memory cell is accessed.