Semiconductor memory device used as a digital buffer and reading and writing method thereof

A data writing and reading method for a semiconductor memory device having memory means comprising memory cells arranged in a matrix comprising n rows and m columns, where m.gtoreq.2 and n.gtoreq.1, each of said memory cells comprising a single port basic cell and being capable of storing a single word of data comprising at least one bit, the data writing and reading method comprising the steps of:

• a) selecting two consecutive memory cells having matrix coordinate values (s, t) and (s+1, t+1) in the matrix, where 1.ltoreq.s.ltoreq.n and 1.ltoreq.t.ltoreq.m, and wherein s+1=when s=n, s-1=n when s=1, t+1=when t=m, and t-1=m when t=1,
• b) reading the single word data stored in one of said two memory cells, the single word data of each of said memory cells being read out cycle by cycle;
• c) writing the single word data in the other of said memory cells during a single cycle, a reading operation performed in the step b) and a writing operation in the step c) are performed during the same cycle;
• d) selecting another set of two memory cells having matrix coordinate values (s, t+1) and (s, t+2), when the reading operation and the writing operation for one cycle are completed, for performing another cycle of the reading operation and the writing operation, wherein s is incremented when t reaches m,
• e) repeating the steps b) to d) for a predetermined number of cycles by incrementing the matrix coordinate values of the two memory cells to be selected.

A semiconductor memory device having memory means comprising memory cells arranged in a matrix comprising n rows and m columns, where m.gtoreq.2 and n.gtoreq.1, each of the memory cells comprising a single port basic cell and being capable of storing a single word data comprising at least one bit, the memory cells arranged in a single column forming a memory cell block, the semiconductor memory device comprising:

• selecting means for selecting one set of two memory cells, one from an arbitrary memory cell block and the other from a different memory cell block, said selecting means including row selecting means for selecting a row on which said two memory cells are located, and column selecting means for selecting at least one memory cell block in which the memory cells to be read and to be written are provided;
• reading means for reading the single word data stored in one of said two memory cells, the single word data of each of the memory cells being read out cycle by cycle, said reading means having read block selecting means connected to each memory cell blocks for selecting in accordance with a read block selection signal a memory cell block in which said one of said two memory cells to be read by said reading means is provided;
• writing means for writing the single word data in the other of the memory cells during a single cycle, said writing means having write block selecting means connected to each memory cell blocks for selecting in accordance with a write block selection signal a memory cell block in which said the other of two memory cells to be written by said writing means is provided;
• said selecting means further including means for sending said write block selection signal to the write block selecting means corresponding to a memory cell block in which said the other of said memory cells to be written is provided, and means for sending said read block selection signal to the read block selecting means corresponding to a memory cell block in which said one of said two memory cells to be read is provided;
• and
• wherein a reading operation performed by the reading means and a writing operation performed by the writing means for the set of two memory cells are performed during the same cycle;
• another set of two memory cells being selected by said selecting means, when the reading operation and the writing operation for one cycle are completed, for performing another cycle of the reading operation and the writing operation, the reading operation and the writing operation being repeated for a predetermined number of cycles.

A semiconductor memory device having memory means comprising memory cells arranged in a matrix comprising n rows and m columns, where m.gtoreq.2 and n.gtoreq.1, each of the memory cells comprising a single port basic cell and being capable of storing a single word data comprising at least one bit, the memory cells arranged in a single column forming a memory cell block, the semiconductor memory device comprising:

• selecting means for selecting one set of two memory cells, one from an arbitrary memory cell block and the other from a different memory cell block, said selecting means including word lines provided to each row of the matrix, a row selection signal being sent from row selecting means to one of said word lines corresponding to the row on which the memory cells to be read and to be written are located, and said selecting means further including sub word line selecting means, provided to each of the memory cells, for activating a sub word line connecting said sub word line selecting means to the corresponding memory cell so that said corresponding memory is activated, said sub word selecting means activating said sub word line when the row selection signal and a block selection signal are supplied thereto at the same time;
• reading means for reading the single word data stored in one of said two memory cells, the single word data of each of the memory cells being read out cycle by cycle;
• and
• writing means for writing the single word data in the other of the memory cells during a single cycle;
• wherein a reading operation performed by the reading means and a writing operation performed by the writing means for the set of two memory cells are performed during the same cycle, another set of two memory cells being selected by said selecting means, when the reading operation and the writing operation for one cycle are completed, for performing another cycle of the reading operation and the writing operation, the reading operation and the writing operation being repeated for a predetermined number of cycles.