US 5,495,440 AGranted

Semiconductor memory device having hierarchical bit line structure

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorMikio Asakura

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Abstract

A memory cell array is divided into a plurality of memory cell groups in the column direction. In each memory cell group, a sub-bit line SBL and a sub-cell plate line SCPL are located. A pair of main bit lines are arranged for memory cells on one column. For each sub-cell plate line, a switching transistor is provided connecting the sub-cell plate line to one main bit line in response to a group select signal. For each sub-bit line, a switching transistor is provided connecting corresponding sub-bit lines to the other main bit line in response to a group select signal BS. A constant voltage VBL is transmitted to the sub-cell plate line through a switching transistor rendered conductive in response to a group select signal CPPR. A dynamic type semiconductor memory device is provided whose memory array layout is facilitated and in which a sufficient read potential difference is produced on a pair of bit lines upon word line selection.

Claims29

Dependent claims

A semiconductor memory device, comprising:

a plurality of memory cells arranged in rows and columns and divided into groups of rows of memory cells, each of said plurality of memory cells including a capacitor having a storage node and a cell plate node for storing data and an access transistor;
a plurality of pairs of main bit lines arranged corresponding to the columns of the memory cells;
a plurality of sub-column lines arranged corresponding to the columns and to the groups of rows of memory cells, each of said sub-column lines connecting the access transistors of a corresponding group on a corresponding column;
a plurality of sub-cell plate lines provided corresponding to said plurality of sub-column lines and connecting the cell plate nodes of capacitors of memory cells of corresponding groups on corresponding columns;
a plurality of first switching means provided for each of said plurality of sub-column lines and responsive to a first group select signal, each for connecting a corresponding sub-column line to one of main bit lines of a corresponding pair of main bit lines;
a plurality of second switching means provided corresponding to said plurality of sub-cell plate lines and each responsive to a second group select signal for connecting a corresponding sub-cell plate line to another main bit line of the corresponding pair of main bit lines;
and
a plurality of third switching means provided corresponding to said plurality of sub-cell plate lines and each responsive to a third group select signal for isolating a corresponding sub-cell plate line from a reference voltage source supplying a predetermined reference voltage for a predetermined time period.

5 more elements

Dependencies are inferred from the claim text.