Non-volatile RAM transferring data between ferro-electric capacitors and a memory cell

#The present invention relates in general to semiconductor memories and, more particularly, to a non-volatile semiconductor memory made with ferro-electric capacitors.

#Semiconductor memories are used in a myriad of applications to store data for later retrieval and usage. Many applications require the memory to be non-volatile in that the data must remain valid for a long period of time even when external power is removed from the memory cell. One such application involves the use of tag memory where one or more memory cells are placed on an item, e.g. personal luggage, that does not have a power source. The tag memory on the luggage may be accessed, for example at airports and depots, to make identification as to the owner and destination. An RF signal is transmitted remotely from a reader to access the tag memory. Some of the received RF transmission signal power energizes the tag memory cell so that the data may be retrieved and transmitted back to the reader. The tag memory must be non-volatile since it remains dormant for long periods of time between accesses.

#In the prior art, ferro-electric capacitors have been used as the non-volatile memory storage element. However, the number of available data accesses is limited because the ferro-electric property degrades with each memory access cycle. Most if not all ferro-electric memory structures drive the ferro-electric material completely around its hysteresis loop every time the ferro-electric memory cell is accessed. Thus, with the ferro-electric capacitors used as the non-volatile memory storage element, the continuous memory cycling leads to an unnecessary amount of polarization domain switching that also causes excessive power consumption by the ferro-electric cell and reduces the endurance and data retention time of the memory circuit.

#FIG. 1 is a schematic diagram illustrating a ferro-electric RAM circuit;

#FIG. 2 is a plot of the hysteresis loop of the ferro-electric capacitors of FIG. 1; and

#FIG. 3 is a waveform plot useful in the explanation of FIG. 1.

#Referring to FIG. 1, a non-volatile RAM circuit 10 is shown receiving control signals ENABLE, WORDLINE, DRIVELINE, and PASSGATE generated by a control circuit (not shown). RAM circuit 10 is useful in applications such as tag memory where one or more memory cells are placed on an item that does not have a power source, for example personal luggage. The tag memory may be accessed with an RF signal transmitted remotely from a reader (not shown). Some of the received RF transmission signal power energizes RAM circuit 10 so that the data may be retrieved and transmitted back to the reader. The tag memory must be non-volatile since it remains dormant for long periods of time between accesses.

#Ferro-electric capacitors 14 and 16 receive the DRIVELINE control signal at one common terminal. Capacitors 14 and 16 are each selected at one picofarad (pf). A second terminal of ferro-electric capacitor 14 is coupled to the source of transistor 18, while a second terminal of ferro-electric capacitor 16 is coupled to the source of transistor 20. The gates of transistors 18 and 20 receive the WORDLINE control signal. The drains of transistors 18 and 20 are coupled to data bitlines 22 and 24, respectively.

#A memory cell 25 includes first and second terminals coupled to data bitlines 22 and 24. Transistors 26 and 28 of memory cell 25 form a first inverter. The gates of transistors 26 and 28 form the first terminal of memory cell 25 that is coupled to data bitline 24. Capacitor 30 is coupled between bitline 24 and power supply conductor 32 operating at ground potential. The drain of transistor 26 is coupled to the drain of transistor 28 at bitline 22, while the source of transistor 28 is coupled to power supply conductor 32. Transistors 34 and 36 of memory cell 25 form a second inverter. The gates of transistors 34 and 36 form the second terminal of memory cell 25 that is coupled to data bitline 22. The drain of transistor 34 is coupled to the drain of transistor 36 which is further coupled to bitline 24. The source of transistor 36 is coupled to power supply conductor 32. Capacitor 38 is coupled between bitline 22 and power supply conductor 32. Capacitors 30 and 38 are each selected at ten pf. Memory cell 25 is enabled by transistor 40 having a drain coupled to the sources of transistors 26 and 34 at node 41, and a source coupled to power supply conductor 42 operating at a positive potential V.sub.DD such as 3.0 volts. Transistors 44 and 46 operate as pass transistors to couple complementary data signals DATA and DATA to bitlines 22 and 24, respectively. The gates of transistors 44 and 46 receive the PASSGATE control signal.