US 5,495,422 A · Method for combining a plurality of independently operating circuits within a single package

Abstract

An integrated circuit has a plurality of interface pins and includes a first circuit block that is comprised of a plurality of gate-equivalent circuits; the first circuit block being a first partition of a data processing system. The integrated circuit further includes at least one other circuit block comprised of a plurality of gate-equivalent circuits; the second circuit block being a second partition of the data processing system. The first and second circuit blocks are capable of operating independently of one another, with each performing an associated function. At least one mode select interface pin is provided, in conjunction with gating circuitry that is interposed between the first and second circuit blocks and the interface pins for selectively coupling, in accordance with a logic level applied to the at least one mode select interface pin, only one of the circuit blocks to the interface pins. A method of specifying a gate array integrated circuit to include a plurality of independently operating circuit blocks is also disclosed.

Claims11

Dependent claims

A method of fabricating an integrated circuit, comprising the steps of:

providing at least two circuit designs;
determining a total number of gates that are required to implement the at least two circuit designs within a gate array;
determining a maximum number of interface terminals that are sufficient to accommodate the interface terminal requirement of the circuit design that has a largest interface terminal requirement;
selecting a gate array type that has a number of gates that is greater than the determined number of gates and that has a number of interface terminals that is sufficient to accommodate the determined maximum number of interface terminals;
translating each of the designs into a gate array equivalent to provide a specification of a gate array circuit block for each of the designs;
defining at least one interface terminal to be a mode select input terminal;
and
determining a gate equivalent circuit of a gating logic block for selectively coupling only one of the circuit blocks to the interface terminals of the gate array in accordance with a logic state of an input signal to be applied to the at least one mode select terminal.

5 more elements

An integrated circuit having a plurality of interface terminals, said integrated circuit being used in the construction of a data processing system that includes at least two partitions, each of said at least two partitions being comprised of circuitry that is necessary to implement at least one circuit block of the data processing system, said integrated circuit comprising:

a first circuit block comprised of a plurality of gate-equivalent circuits, said first circuit block comprising said first partition of the data processing system;
at least one other circuit block comprised of a plurality of gate-equivalent circuits, said at least one other circuit block comprising said second partition of the data processing system;
at least one control interface terminal;
and
gating means interposed between said first and second circuit blocks and said interface terminals for selectively coupling, in accordance with a logic level applied to said at least one control interface terminal, only one of said circuit blocks to said interface terminals, whereby a first one of the integrated circuits is used at one location on a circuit board substrate for implementing the circuitry of the first partition and a second one of the integrated circuits is used at another location on the circuit board substrate for implementing the circuitry of the second partition, in accordance with the logic level applied to said at least one control interface terminal at said first and second locations.

2 more elements

a first circuit block comprised of a plurality of gate-equivalent circuits, said first circuit block comprising said first partition of the data processing system, said first partition comprising means for buffering addresses received from the central processor (CP) and addresses received from the IO controller (IOC) before application of the addresses to the main memory;
a second circuit block comprised of a plurality of gate-equivalent circuits, said second circuit block comprising said second partition of the data processing system and including means for buffering data received from the central processor (CP) and data received from the IO controller (IOC) before application of the data to the main memory;
at least two control interface terminals;
and
gating means interposed between said first and second circuit blocks and said interface terminals for selectively coupling in accordance with logic levels applied to at least one of said at least two control interface terminals, when installed upon a printed circuit board, only one of said circuit blocks to said interface terminals for connecting the selected circuit block to the CP, to the IOC, and to the main memory, whereby a first one of the integrated circuits is used at a first location on the printed circuit board for implementing the circuitry of the first partition and a second one of the integrated circuits is used at a second location for implementing the circuitry of the second partition, in accordance with the logic level applied to said at least one of said at least two control interface terminals.

2 more elements

A data processing system comprised of a central processing unit, a memory for storing data, and a bus for coupling said central processing unit to said memory, the bus including a plurality of signal lines for conveying at least memory addresses from said central processing unit to said memory and for conveying data bidirectionally between said central processing unit and said memory, said data processing system further comprising bus interface circuitry that is interposed within said bus between said central processing unit and said memory, said bus interface circuitry comprising address interface circuitry and data interface circuitry, wherein said address interface circuitry and said data interface circuitry are disposed within a single integrated circuit package having a plurality of interface terminals and at least one control input terminal, wherein said plurality of interface terminals and said at least one control terminal of each of a plurality of said integrated circuit packages are electrically coupled to circuit wiring of at least one printed circuit board, wherein said at least one control terminal of a first one of said plurality of integrated circuit packages is electrically coupled to a first logic potential for selecting only said address interface circuitry to be coupled to said plurality of interface terminals and, through said plurality of interface terminals, to circuit wiring that is electrically coupled to said address signal lines;

and wherein said at least one control terminal of a second one of said plurality of integrated circuit packages is electrically coupled to a second logic potential for selecting only said data interface circuitry to be coupled to said plurality of interface terminals and, through said plurality of interface terminals, to circuit wiring that is electrically coupled to said data signal lines.

Dependencies are inferred from the claim text.

Method for combining a plurality of independently operating circuits within a single package

Life of this patent

Method for combining a plurality of independently operating circuits within a single package

Life of this patent

Abstract

Claims11