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US 5,495,382 AGranted
Contents addressable memory
AssigneePlessey Semiconductors Limited
InventorRichard Albon
Life of this patent
Estimating the term…
Abstract
A contents addressable memory comprising an array of contents addressable memory cells arranged in rows and columns, each row of the array having a respective case between address bit values of a data word or words to be retrieved from the memory and bit values held by the cells of the respective row, and a chain of cells associated one with each match line to indicate which, if there are more than one, of the match lines indicating a match is of the highest priority.
Claims4
A contents addressable memory, comprising:
- an array of memory cells arranged in rows and columns, means for applying address bit values to respective columns of said memory cells for comparison with bit values held by said cells, each row having a respective match line circuit means associated therewith for indicting a match or a mis-match between said applied address bit values and the bit values held by said row, a priority encoder means for determining which of a plurality of said match line circuit means indicating matches along the respective rows has the highest priority, said priority encoder means including a plurality of transmission gates associated one with each match line circuit means, means for connecting said transmission gates in series with one another in a series path, respective latch means for enabling operation of each said transmission gate, and means operative for biasing off those transmission gates associated with said match line circuit means in respect of which a match is indicated.
Dependencies are inferred from the claim text.