Digital signal processing circuit for filtering an image signal vertically

A vertical filter for receiving a plurality of horizontal data lines as an input signal and for producing a first filtered signal and a second filtered signal of said input signal, comprising:

• a first adder, a first multiplexer, and a second adder each receiving as an input said input signal;
• a delay circuit for receiving and storing an output of said first multiplexer, said delay circuit producing an output which is received by said first adder and said second adder;
• a second multiplexer having as its inputs said output of said delay circuit and an output of said first adder, an output of said second multiplexer being an input to said first multiplexer;
• a third multiplexer having as its input said output of said delay circuit and an output of said second adder;
• a first control means controlling said second multiplexer to output either said output of said first adder or the contents of said delay circuit;
• a second control means for switching said first multiplexer to output either said input signal or said second multiplexer output alternately at each horizontal line of data of said input signal;
• a third control means for controlling said third multiplexer to output said output of said second adder when said second multiplexer outputs said output of said first adder and for controlling said third multiplexer to output, when said second multiplexer outputs said delay circuit contents, said output of said second adder when said first multiplexer outputs said input signal and said third multiplexer to output said delay circuit contents when said first multiplexer outputs said delay circuit contents.