Fit solid state image sensor with flicker suppression

An FIT solid state image sensor, comprising:

• an image section having an array of photosensitive elements for generating signal charges corresponding to an optical image;
• a storage section for temporarily storing the signal charges transferred from the image section;
• a plurality of vertical shift registers provided for respective vertical lines of the array for vertically transferring the signal charges from the image section through the storage section;
• a horizontal shift register for horizontally transferring the signal charges transferred vertically through the image and storage sections by the vertical shift registers;
• and
• means for applying clock pulses to the vertical shift registers during a line shift transfer period for transferring the signal charges from the image section, through the storage section, and to the horizontal shift register;
• wherein said applying means applies said clock pulses to said transfer electrodes of said vertical shift registers in said image section such that the photosensitive elements arranged in odd horizontal lines of the array receive a potential from said vertical shift registers which is equal to a potential received by the photosensitive elements arranged in even horizontal lines of the array from said vertical shift registers;
• whereby the vertical shift registers of the image section are controlled to prevent flicker when no light is incident on the image section;
• wherein each of the vertical shift registers has a pair of transfer electrodes for one of the photosensitive elements arranged in a vertical line of the array, adjacent four transfer electrodes constituting one stage, four phase clock pulses .PHI.IM1, .PHI.IM2, .PHI.IM3, and .PHI.IM4 being applied to the four transfer electrodes in a sequence of transferring signal charges so as to read one frame of signal charges;
• and
• wherein all of the four phase clock pulses .PHI.IM1, .PHI.IM2, .PHI.IM3 and .PHI.IM4 are held at a constant low voltage level during the line shift transfer period.

An FIT solid state image sensor, comprising:

• an image section having an array of photosensitive elements for generating signal charges corresponding to an optical image;
• a storage section for temporarily storing the signal charges transferred from the image section;
• a plurality of vertical shift registers provided for respective vertical lines of the array for vertically transferring the signal charges from the image section through the storage section;
• a horizontal shift register for horizontally transferring the signal charges transferred vertically through the image and storage sections by the vertical shift registers;
• and
• means for applying clock pulses to the vertical shift registers during a line shift transfer period for transferring the signal charges from the image section, through the storage section, and to the horizontal shift register;
• wherein said applying means applies said clock pulses to said transfer electrodes of said vertical shift registers in said image section such that the photosensitive elements arranged in odd horizontal lines of the array receive a potential from said vertical shift registers which is equal to a potential received by the photosensitive elements arranged in even horizontal lines of the array from said vertical shift registers;
• whereby the vertical shift registers of the image section are controlled to prevent flicker when no light is incident on the image section;
• wherein each of the vertical shift registers has a pair of transfer electrodes for one of the photosensitive elements arranged in a vertical line of the array, adjacent four transfer electrodes Constituting one stage, four phase clock pulses .PHI.IM1, .PHI.IM2, .PHI.IM3 and .PHI.IM4 being applied to the four transfer electrodes in a sequence of transferring signal charges so as to read one frame of signal charges;
• and
• wherein all of the four phase clock pulses .PHI.IM1, .PHI.IM2, .PHI.IM3 and .PHI.IM4 are held at a constant high voltage level during the line shift transfer period.

A frame interline transfer (FIT) type CCD image sensor, comprising:

• an image section which includes an n.times.m array of photosensitive elements arranged in m horizontal lines and n vertical lines of the array and associated with respective vertical shift registers driven by a plurality of image section clock pulses, each of the vertical shift registers having a pair of transfer electrodes for each one of the photosensitive elements arranged in a vertical line of the array, said plurality of image section clock pulses being applied to respective pairs of said transfer electrodes for transferring signal changes through said image section;
• a charge storage section through which said vertical shift registers extend for temporarily storing signal charges transferred thereto from the image section by the vertical shift registers, said vertical shift registers being driven by a plurality of storage section clock pulses;
• a horizontal shift register for receiving signal charges from said charge storage section at uniform intervals and driven by a plurality of horizontal shift register clock pulses;
• a signal charge detecting section connected to said horizontal shift register for converting signal charges transferred thereto into a video signal;
• wherein said image section clock pulses are set so that during a line shift transfer period the photosensitive elements arranged in the odd horizontal lines of the array receive a potential from said vertical shift registers which is equal to a potential received by the photosensitive elements arranged in the even horizontal lines of the array from the vertical shift registers, thus preventing flicker noises in a dark condition with no light incident on the image section.

A frame interline transfer (FIT) type CCD image sensor comprising:

• an image section which includes an n.times.m array of photosensitive elements arranged in m horizontal lines and n vertical lines of the array and associated with respective vertical shift registers driven by a plurality of image section clock pulses, each of the vertical shift registers having a pair of transfer electrodes for each one of the photosensitive elements arranged in a vertical line of the array, said plurality of image section clock pulses being applied to respective pairs of said transfer electrodes for transferring signal changes through said image section;
• a charge storage section, through which said vertical shift registers extend, for temporarily storing signal charges transferred thereto from the image section by the vertical shift registers, said vertical shift registers being driven by a plurality of storage section clock pulses;
• a horizontal shift register for receiving signal charges from said charge storage section at uniform intervals and driven by a plurality of horizontal shift register clock pulses;
• a signal charge detecting section connected to said horizontal shift register for converting signal charges transferred thereto into a video signal;
• wherein said image section clock pulses are set so that during a line shift transfer period the photosensitive elements arranged in the odd horizontal lines of the array receive a potential from said vertical shift registers which is equal to a potential received by the photosensitive elements arranged in the even horizontal lines of the array from the vertical shift registers, thus preventing flicker noises in a dark condition with no light incident on the image section;
• wherein each of the vertical shift registers has a pair of transfer electrodes for one of the photosensitive elements arranged in a vertical line of the array, adjacent four transfer electrodes constituting one stage, four phase clock pulses .PHI.IM1, .PHI.IM2, .PHI.IM3 and .PHI.IM4 being applied to the four transfer electrodes in a sequence of transferring signal charges so as to read one frame of signal charges;
• and
• wherein all of the four phase clock pulses .PHI.IM1, .PHI.IM2, .PHI.IM3 and .PHI.IM4 are held at a constant low voltage level during the line shift transfer period.

A frame interline transfer (FIT) type CCD image sensor, comprising:

• an image section which includes an n.times.m array of photosensitive elements arranged in m horizontal lines and n vertical lines of the array and associated with respective vertical shift registers driven by a plurality of image section clock pulses, each of the vertical shift registers having a pair of transfer electrodes for each one of the photosensitive elements arranged in a vertical line of the array, said plurality of image section clock pulses being applied to respective pairs of said transfer electrodes for transferring signal charges through said image section;
• a charge storage section, through which said vertical shift registers extend, for temporarily storing signal charges transferred thereto from the image section by the vertical shift registers, said vertical shift registers being driven by a plurality of storage section clock pulses;
• a horizontal shift register for receiving signal charges from said charge storage section at uniform intervals and driven by a plurality of horizontal shift register clock pulses;
• a signal charge detecting section connected to said horizontal shift register for converting signal charges transferred thereto into a video signal;
• wherein said image section clock pulses are set so that during a line shift transfer period the photosensitive elements arranged in the odd horizontal lines of the array receive a potential from said vertical shift registers which is equal to a potential received by the photosensitive elements arranged in the even horizontal lines of the array from the vertical shift registers, thus preventing flicker noises in a dark condition with no light incident on the image section;
• wherein each of the vertical shift registers has a pair of transfer electrodes for one of the photosensitive elements arranged in a vertical line of the array, adjacent four transfer electrodes constituting one stage, four phase clock pulses .PHI.IM1, .PHI.IM2, .PHI.IM3 and .PHI.IM4 being applied to the four transfer electrodes in a sequence of transferring signal charges so as to read one frame of signal charges;
• and
• wherein all of the four phase clock pulses .PHI.IM1, .PHI.IM2, .PHI.IM3 and .PHI.IM4 are held at a constant high voltage level during the line shift transfer period.