US 5,495,245 AGranted

Digital-to-analog converter with segmented resistor string

AssigneeAnalog Devices, Inc.

InventorJames J. Ashe

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Abstract

The number of resistors and switches required for a voltage-scaling digital-to-analog converter (DAC) is greatly reduced by segmenting the voltage decrementing resistor string into two separate outer strings and an inner string. The outer strings decrement a full-scale voltage in accordance with the most significant bits (MSBs) of the input digital signal, while the inner string decrements the least significant bits (LSBs); alternately, the outer strings can decrement the LSBs and the inner string the MSBs. Opposite ends of the inner string are connected to corresponding points on the two outer strings through passive switched taps on the outer strings that allow the DAC to function as a potentiometer or rheostat, and "slide" up and down along the two outer strings as the input digital signal varies. An analog output is tapped from a selected point on the inner string whose voltage elevation is controlled by the switching of the outer strings. The outer strings are preferably switched in a sequence that adds a transient finite resistance to the circuit during switching, but avoids large scale glitches due to open circuits or short circuiting part of the string.

Claims15

Dependent claims

A segmented digital-to-analog converter (DAC) for an N-bit digital signal, comprising:

high and low analog reference voltage nodes,
an analog output node,
first and second separate outer strings of respective predetermined series connected resistors, one end of the first outer resistor string being connected to said high reference voltage node and one end of the second outer resistor string being connected to the low reference voltage node, the resistors of each outer string being connected directly in series,
an inner string of series connected resistors,
first and second outer switch networks connected respectively to said first and second outer resistor strings to provide selectable unbuffered taps from said outer resistor strings to opposite ends of said inner resistor string,
an inner switch network connected to said inner resistor string to provide a selectable tap from said inner resistor string to said output node, and
a decoder which responds to an input digital signal by controlling said first and second outer switch networks to switch selectable portions of said outer resistor strings into a series connection with said inner resistor string, the selected portions having a substantially constant aggregate series resistance over the switching ranges of said outer switch networks, said decoder further controlling said inner switch network to tap said inner resistor string at a location whose analog voltage level corresponds to said digital input signal,
the number and resistance values of the resistors in said outer resistor strings decrementing the voltage between said high and low reference voltage nodes in a manner that corresponds to either the most significant bits (MSBs) or the least significant bits (LSBs) of said input digital signal, and the number and resistance values of the resistors in said inner resistor string decrementing the voltage between said outer resistor strings in a manner that corresponds to the other of said MSBs and LSBs.

5 more elements

A digital-to-analog converter (DAC) for an n-bit digital signal comprised of most significant bits (MSBs) and least significant bits (LSBs), comprising:

high and low reference voltage nodes,
a pair of separate outer resistor strings having respective predetermined resistors, with one end of each string connected to a respective reference voltage node, both of said outer resistor strings decrementing an applied voltage in accordance with either a MSB or a LSB pattern, and including taps at corresponding decremented MSB or LSB locations along the string, the resistors of each outer being connected directly in series,
an inner resistor string for decrementing an applied voltage in accordance with the LSB or MSB pattern that is not used by said outer strings, and including selectable output taps at corresponding decremented LSB or MSB locations along the string,
a switch network connecting said inner resistor string between selectable unbuffered taps of said outer resistor strings so that the total resistance between said high and low voltage reference nodes remains constant for all switch selections, and
a decoder connected to receive an input digital signal and to select a switch network configuration and an output tap from said inner resistor string that yield a corresponding analog signal at the selected inner resistor string tap.

2 more elements

Dependencies are inferred from the claim text.