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US 5,495,228 AGranted
Fail-safe scan circuit and a multibeam sensor
AssigneeThe Nippon Signal Co., Ltd.
InventorsKoichi Futsuhara, Masakazu Kato
Life of this patent
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Abstract
A fail-safe scan circuit sequentially and periodically drives and scans objective devices. The scan circuit has a failure detector that provides, upon detecting a failure, a signal of logical value 0 to inform of the failure. Adjacent input signals to the failure detector have a phase difference of .pi.. This phase difference results in simplifying the structure of the failure detector. The fail-safe scan circuit is employable to drive and scan many photosensors of a fail-safe multibeam sensor.
Claims15
A fail-safe circuit for sequentially and periodically driving and scanning objective devices, comprising:
- a counter circuit for periodically counting as many pulses of an input clock signal as the objective devices;
- a scan signal generator for consecutively generating as many scan signals as the objective devices in response to count signals provided by the counter circuit;
- and
- a fail-safe failure detector for generating a signal of logical value 1 corresponding to a high energy state if the scan signals are normal, and a signal of logical value 0 corresponding to a low energy state to indicate an abnormality not only when some of the scan signals overlap or at least one of the scan signals is missed in a scan period but also when some of the scan signals overlap and at least one of the scan signals is missed in a scan period,
- the fail-safe failure detector having;
- a first detective function unit involving a first adder, for determining whether or not some of the scan signals are overlapping according to an output of the first adder, and if they are overlapping, providing a signal of logical value 0 to indicate the abnormality;
- a second detective function unit for determining whether or not all scan signals to be generated in a scan period have been completely generated, and if at least one of them has not been generated, providing a signal of logical value 0 to indicate the abnormality;
- an AND circuit for providing an AND of the outputs of the first and second detective function units;
- and
- an ON delay circuit for providing a signal of logical value 1 to indicate that the scan signals are normal a delay time, which is longer than the scan period, after receiving a signal of logical value 1 from the AND circuit,
- the first adder of the first detective function unit having:
- input terminals for receiving the scan signals, respectively, the scan signals being sequentially generated by the scan signal generator with any adjacent two of them having a phase difference of .pi.;
- capacitors series-connected to the input terminals, respectively, for transmitting the scan signals to an output terminal and smoothing scan signals of the next scan period;
- clamp diodes provided for the capacitors, respectively, to clamp outputs of the capacitors to a predetermined voltage;
- a clamp diode for clamping the output terminal to the predetermined voltage;
- and
- a smoothing capacitor for smoothing a voltage appearing at the output terminal,
- the first adder doubling, rectifying and summing up the voltages of the scan signals with a chargeischarge time constant for the voltage doubling and rectifying processes being set according to a period of a scan signal.
15 more elements
A fail-safe scan circuit for sequentially and periodically driving and scanning objective devices, comprising:
- a counter circuit for periodically counting as many pulses of an input clock signal as the objective devices;
- a scan signal generator for consecutively generating as many scan signals as the objective devices in response to count signals provided by the counter circuit;
- and
- a fail-safe failure detector for generating a first signal of logical value 1 corresponding to a high energy state if the scan signals are normal, and a second signal of logical value 0 corresponding to a low energy state to indicate an abnormality not only when some of the scan signals overlap at least one of scan signals is missed in a scan period but also when some of the scan signals overlap and at least one of the scan signals is missed in a scan period,
- the fail-safe failure detector providing the second signal of logical value 0 if at least one of the scan signals is abnormal and the failure detector itself is out of order.
2 more elements
Dependencies are inferred from the claim text.