Fractional N frequency synthesis with residual error correction and method thereof
AssigneeMotorola, Inc.
InventorAlexander W. Hietala
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AssigneeMotorola, Inc.
InventorAlexander W. Hietala
Estimating the term…
A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).
A frequency synthesizer having a controllable oscillator for generating a first signal having a first frequency, the frequency synthesizer comprising:
A fractional-N frequency synthesizer accepting a first signal to select a controllable oscillator output signal frequency by dividing the output signal frequency with a variable divisor divider controlled by a divider sequence signal from an accumulator network creating a divided signal, the divider sequence signal containing a desired value and an error value, the fractional-N synthesizer comprising:
A fractional-N frequency synthesizer comprising:
A method of frequency synthesizing, the frequency synthesizer having a controllable oscillator for generating a first signal having a first frequency, the method comprising the steps of:
Dependencies are inferred from the claim text.