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US 5,495,199 AGranted
Switched capacitor circuit
AssigneeNippondenso Co., Ltd.
InventorTetsuo Hirano
Life of this patent
Estimating the term…
Abstract
A switched capacitor circuit includes a capacitor, a MOS switch and a timing generating circuit. The MOS switch is connected with the capacitor in series for discharging electric charges which are charged into the capacitor. The MOS switch includes a plurality of MOS transistors which are parallelly connected with each other. The timing generating circuit generates timing signals to the MOS switch so that the MOS transistors are turned on one after another in response to each timing signal. Sampling noise is reduced because an ON-state resistance of the MOS switch is transiently high.
Claims14
A switched capacitor circuit comprising:
- a capacitor for storing electric charges;
- MOS switching means for discharging said electric charges, said MOS switching means having a predetermined gate width and including a plurality of MOS transistors connected in parallel with each other, each transistor having a specific gate width, wherein said predetermined gate width is divided among said specific gate widths of said plurality of MOS transistors such that a sum of said specific gate widths corresponds to said predetermined gate width;
- and
- timing generating means for cyclically generating a plurality of predetermined timing signals to turn on said plurality of MOS transistors one after another for increasing an on-state resistance of said MOS switching means at a transient period thereof when said MOS switching means is turned on, and to turn off said plurality of MOS transistors simultaneously when said MOS switching means is turned off.
1 more element
A switched capacitor circuit comprising:
- a capacitor for storing electric charges;
- a charging circuit for charging said capacitor, said charging circuit including:
- a first MOS switch device, said first MOS switch device having a first predetermined gate width and including a plurality of MOS transistors, each transistor having a specific gate width, said transistor being connected in parallel with each other, wherein said predetermined gate width is divided among said specific gate widths of said plurality of MOS transistors such that a sum of said specific gate widths corresponds to said predetermined gate width;
- a discharging circuit for discharging said capacitor, said discharging circuit including:
- a second MOS switch device, said second MOS switch device having a second predetermined gate width and including a plurality of MOS transistors, each transistor having said specific gate width and connected in parallel with each other, wherein a number of said MOS transistors included in said second MOS switch device is the same as a number of said MOS transistors included in said first MOS switch device;
- and
- timing generating means for cyclically generating a plurality of predetermined timing signals to control said first MOS switch device for charging said capacitor so as to turn on said plurality of MOS transistors included in said first MOS switch device in a first sequential order and so as to turn off said plurality of MOS transistors included in said first MOS switch device simultaneously, and to control said second MOS switch device for discharging said capacitor so as to turn on said plurality of MOS transistors included in said second MOS switch device in a second sequential order and so as to turn off said plurality of MOS transistors included in said second MOS switch device simultaneously.
4 more elements
A switched capacitor circuit comprising:
- a capacitor;
- a charging circuit for charging said capacitor, said charging circuit including:
- a first MOS switch device including two complementary MOS transistors connected in parallel, and
- a second MOS switch device including two complementary MOS transistors connected in parallel;
- a discharging circuit for discharging said capacitor, said discharging circuit including:
- a third MOS switch device including two complementary MOS transistors connected in parallel, and
- a fourth MOS switch device including two complementary MOS transistors connected in parallel, wherein said complementary MOS transistor included in said first, second, third and fourth MOS switch devices have a same size gate width;
- and
- timing generating means for cyclically generating a plurality of predetermined timing signals to sequentially turn on said complementary MOS transistors included in said first and said second MOS switch devices for charging said capacitor, to turn off said complementary MOS transistors included in said first and said second MOS switch devices simultaneously, to turn on said complementary MOS transistors included in said third and fourth MOS switch devices for discharging said capacitor, to turn off said complementary MOS transistors included in said third and fourth MOS switch devices simultaneously.
6 more elements
Dependencies are inferred from the claim text.