Variable delay circuit

Abstract

First and second exclusive-OR gates (hereinafter referred to as EXOR gates) are provided, which are both connected at one input side to a delay input terminal. The other input side of the first EXOR gate is grounded and the other input side of the second EXOR gate is connected to a select signal input terminal. A capacitor is connected between the output side of the first EXOR gate and the output side of the second EXOR gate. The output side of the first EXOR gate is connected to a delay output terminal by way of a buffer which outputs logical levels. The buffer has a threshold value and outputs one or the other binary logical level depending on whether the input thereto is above or below a threshold value.

Dependencies are inferred from the claim text.