Output buffer for a high density programmable logic device

Abstract

An output buffer circuit for a high density programmable logic device. The output buffer includes inverters having n-channel pull up and pull down transistors for driving pull up and pull down transistors providing the buffer output. By utilizing inverters with n-channel replacing p-channel transistors, crowbar resulting from a different number of inverters required to drive the pull up and pull down transistors which provide the buffer output is prevented. By utilizing n-channel rather than p-channel transistors, mobility is increased and Miller capacitance is reduced, reducing loading of the buffer input. To provide the rail-to-rail voltage of p-channel transistors which can further increase switching speed, p-channel pull up transistors are provided with circuitry to turn the p-channel transistors on after the n-channel transistors have turned on and turn the p-channel transistors off after the buffer output switches. To further increase switching speed, the buffer includes circuitry to reduce voltage on the gates of the pull up or pull down transistors providing the buffer output after the p-channel transistor driving its gate turns off. To enable control of additional power consumption occurring with increased buffer operation speed, the buffer provides a selectable fast/slow mode wherein features of the buffer which increase operation speed may be selectively enabled or disabled.

Dependencies are inferred from the claim text.