Single ended dynamic sense amplifier

A computer system comprising:

• a memory;
• and
• a processor coupled to the memory, the processor including a register file having a memory location and a sense amplifier circuit coupled to the memory location via a first node, the sense amplifier circuit for determining a state of the memory location, the sense amplifier circuit including:
• an output circuit having an input and an output, the output for indicating a state of the memory location in response to a node voltage level of the first node;
• a precharge circuit coupled to the input, the precharge circuit for charging the input to a first voltage level;
• a discharge circuit coupled to the first node and the input, the discharge circuit for discharging the input from the first voltage level to the node voltage level, wherein the discharge circuit comprises:
• a first inverter coupled to the first node, the first inverter for outputting a discharge input voltage by inverting the node voltage of the first node;
• a first field effect transistor (FET) having a drain, a source, and a gate, wherein the drain is coupled to the input, the source is coupled to the first node, and the gate is coupled to receive the discharge input voltage, the first FET for coupling the input to the first node when the discharge input voltage exceeds a first threshold voltage of the first FET;
• a noise margin circuit coupled to the first node, the noise margin circuit for charging the first node to the node voltage level that is less than the first voltage level such that the discharge input voltage level is less than the first threshold voltage level by a predetermined noise margin voltage, wherein the noise margin circuit comprises:
• a second inverter coupled to the first node, the second inverter for outputting a second voltage by inverting the node voltage of the first node;
• and
• a second FET having a drain, a source, and a gate coupled to receive the second voltage, the second FET for charging said first node towards the first voltage level until the second voltage drops to a second threshold voltage of the second FET wherein the noise margin voltage is determined by a period of time during which the second FET remains switched on after the first FET is switched off.