Arbiter circuit
AssigneeTexas Instruments Incorporated
InventorsKeiichiroh Abe, Souichirou Kamei
Life of this patent
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Abstract
An arbiter circuit for determining priority as between two or more competing request signals and applicable for use in a memory system having a number of memories operating independently without interfering with one another. For each of a number of memories, a receiving circuit 10(i) and an arbitration circuit 12(i) with standardized configurations are allotted. Common memory cycle clock pulse ARB-CLK is sent from memory cycle generator 16 to all of arbiter units 14(1)-14(N) . From the arbiter units 14(1)-14(N) , the commands for the respective memories are output in synchronization to each other based on memory cycle clock pulse ARB-CLK.
Claims7
A common arbiter circuit for a plurality of memories, for arbitrating for each memory among a corresponding plurality of competing request signals received by the common arbiter circuit for that memory, comprising:
- (a) a common memory cycle generator for generating a common clock pulse signal;
- and
- (b) for each memory, a corresponding separate arbiter unit for (i) receiving the common clock pulse signal and the corresponding plurality of competing request signals for that memory, (ii) determining which of the competing request signals has priority, and (iii) generating a corresponding timing command for the corresponding memory, at times designated by the common clock pulse signal;
- whereby the common arbiter circuit enables the memories to operate simultaneously but independently.
A common arbiter circuit for a plurality of memories, for arbitrating for each memory among a corresponding plurality of competing request signals received by the common arbiter circuit for that memory, comprising:
- (a) a common memory cycle generator for generating a common clock pulse signal;
- and
- (b) for each memory a corresponding separate arbiter unit having:
- a receiving circuit coupled to receive (i) the common clock pulse signal, (ii) the corresponding plurality of competing request signals for that memory, and (iii) a feedback signal for that memory, and
- an arbitration circuit, coupled to receive (i) the common clock pulse signal from the common memory cycle generator and (ii) the plurality of competing request signals from the receiving circuit, for determining which of the competing request signals has priority and generating a corresponding timing command for transmission to the corresponding memory and receiving circuit, at times designated by the common clock pulse signal;
- whereby the common arbiter circuit enables the memories to operate simultaneously but independently.
A method of simultaneously arbitrating, for a plurality of memories, among a plurality of competing request signals received for each memory, comprising the steps of:
- (a) generating a common clock pulse signal;
- (b) for each memory, at times designated simultaneously for all the memories by the common clock pulse:
- (i) independently determining which of the competing request signals for that memory has priority, and
- (ii) generating a corresponding separate timing command for the corresponding memory.
Dependencies are inferred from the claim text.