Non-overlap signal generation circuit

A non-overlap signal generation circuit for a semiconductor memory device which generates two non-overlapped output signals of complementary logic levels with respect to one input signal, comprising:

• a first data path including a first transistor for transiting a first output node from logic "0" to logic "1" when said iput signal is transited from logic "0" to logic "1", whereas from logic "1" to logic "0" when said input signal is transited from logic "1" to logic "0", a first inverter for inverting said input signal, and a second transistor for transiting said first output node from logic "1" to logic "0" in response to an output signal from said first inverter;
• and
• a second data path including a third transistor for transiting a second output node from logic "0" to logic "1" when the output signal from said first inverter is transited from logic "0" to logic "1", whereas from logic "1" to logic "0" when the output signal from said first inverter is transited from logic "1" to logic "0", a second inverter for inverting the output signal from said first inverter, and a fourth transistor for transiting said second output node from logic "1" to logic "0" in response to an output signal from said second inverter;
• whereby said two non-overlapped output signals are generated according to a time difference between said first and second data paths.