Back to results
US 5,495,188 AGranted
Pulsed static CMOS circuit
AssigneeInternational Business Machines Corporation
InventorsChih-Liang Chen, Gary S. Ditlow
Life of this patent
Estimating the term…
Abstract
A pulsed static CMOS circuit. Improved static CMOS circuit speed is achieved without using a clock scheme like that in dynamic CMOS circuits. The disclosed circuit family is a pulsed static CMOS circuit which makes only a single transition during evaluation. The circuit is reset to a predetermined state by an input pattern, which is in favor of the faster switching direction of the static CMOS.
Claims8
An electrical logic circuit, comprising:
- a first dynamic latch having a data input and a system clock input, the dynamic latch producing a pulsed output characterized by an evaluate edge and a data reset edge;
- a logic circuit coupled to receive the pulsed output of the first dynamic latch, the logic circuit comprising means for producing a pulsed output signal, one edge of which comprises evaluate information, the logic circuit being characterized in that it has no clock input;
- a second dynamic latch coupled to receive the pulsed output from the logic circuit.
Dependencies are inferred from the claim text.