US 5,495,184 AGranted

High-speed low-power CMOS PECL I/O transmitter

AssigneeVLSI Technology, Inc.

InventorsAndre P. Des Rosiers, Paul D. Ta

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Abstract

An output buffer contains a totem-pole structure of four CMOS transistors. The top two are PMOS devices and the bottom two are NMOS devices. The top and bottom transistors function as output current switches which alternatively turn on and off the current flow from either VSS or VDD to the resistive termination load Rt. The middle two devices are connected to DC voltage references which control a precise amounts of current sourced to a load using a precision current source and sunk from a load using and to a precision current sink. The reference voltages for the precision current source and the current sink uses a negative feedback circuit which is referenced to a resistor ladder and a current source controlled by a band-gap reference source. This allows for on-chip referencing of ECL levels and control of reference voltages and currents in spite of variation is process, voltage, and temperature. Internal ECL reference levels signals V.sub.OL and V.sub.OH are used to control the output levels. Operational amplifiers drive the respective transistors such that voltage at the drains of the current source and sink transistors equals the ECL reference inputs VOH and VOL. These control voltages generate a precise currents through a replica stage and are also applied to the output stage. All of the devices in the reference control circuit are scaled to reduce DC power dissipation. For differential operation, a second totem-pole driver circuit is used with the inverse input data signal for controlling the output current switches.

An output driver circuit, comprising:

a first termination resistance R.sub.T1 which has one terminal connected to a first output terminal of the output driver circuit and which has the other terminal connected to a termination voltage source V.sub.T ;
a first PMOS switch transistor M1, having a drain terminal, a source terminal, and a gate terminal, wherein said source terminal is connected to a V.sub.DD voltage source;
first switch means for providing a first switching signal to the gate terminal of the first PMOS switch transistor M1 for turning on and off current flow from the V.sub.DD voltage source through the first PMOS switch transistor M1;
a second PMOS current-source transistor M2, having a drain terminal, a source terminal, and a gate terminal, wherein the source terminal of the second PMOS current-source transistor M2 is connected to the drain terminal of the first PMOS switch transistor M1 and wherein the source terminal of the second PMOS current-source transistor M2 is connected to the first output terminal of the output driver circuit;
a first DC voltage reference source REF A having an output terminal connected to the gate terminal of the second PMOS current-source transistor M2 for controlling the amount of current provided by the second PMOS current-source transistor M2 to the first termination resistance R.sub.T1 ;
a first NMOS current-sink transistor M3, having a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is connected to the drain terminal of the second PMOS current-source transistor M2 and to the first output terminal of the output driver circuit;
a second DC voltage reference source REF B having an output terminal connected to the gate terminal of the first NMOS current-sink transistor M3 for controlling the amount of current provided from the first termination resistance R.sub.T1 to the first NMOS current-sink transistor M3;
a second NMOS switch transistor M4, having a drain terminal, a source terminal, and a gate terminal, said source terminal being connected to a V.sub.SS voltage source, wherein the drain terminal of the second NMOS switch transistor M4 is connected to the source terminal of the first NMOS current-sink transistor M3 and wherein the source terminal of the second NMOS switch transistor N4 is connected to the V.sub.SS voltage source;
and
second switch means for providing a second switching signal to the gate terminal of the second NMOS switch transistor M4 for turning off and on current flow to the V.sub.SS voltage source through the second NMOS switch transistor M4.

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Abstract

Claims11