Stacked ferroelectric memory cell

An integrated circuit array of memory cells where each memory cell includes a ferroelectric capacitor and a transistor, and where each cell is connected to a corresponding bit line, word line, and plate line, the array comprising:

• a plurality of bit lines, each extending along a first direction, each bit line crossing over first and second source/drain regions for at least one transistor, and making electrical contact with said first source/drain region;
• a plurality of word lines, each extending along a second direction, crossing under said plurality of bit lines;
• a first insulation layer covering the tops of said word lines in each memory cell through which the word lines pass;
• a plurality of plate lines, each extending parallel to a corresponding one of the word lines, but separated therefrom by the first insulation layer, each plate line forming a bottom electrode in each cell through which the plate line extends;
• a plurality of ferroelectric dielectric lines parallel to the plate lines, each ferroelectric line being located on top of a respective plate line;
• a plurality of top electrodes, each top electrode contacting an upper surface of a corresponding ferroelectric line;
• a plurality of local interconnects, each memory cell having a respective local interconnect in full contact with a top surface of its corresponding top electrode so that the top electrode is fully covered by the local interconnect, the local interconnect also extending laterally along the first direction and downward to make electrical contact with said second source/drain region via a first contact window, the local interconnect and first contact window being situated beneath a corresponding bit line, the local interconnect having a common lateral edge self-aligned with an edge of the corresponding top electrode;
• the plate lines, ferroelectric dielectric lines, and top electrodes forming a plurality of ferroelectric capacitors located substantially at each intersection of a said bit line and a said word line, the bit lines extending over the ferroelectric capacitors;
• wherein the plate lines, ferroelectric lines, bit lines, and word lines extend to respective pluralities of said memory cells.

A compact memory cell arrangement for an integrated circuit where the memory cell includes a ferroelectric capacitor and a transistor, and where the cell is connected to a bit line, a word line, and a plate line, the arrangement comprising:

• a substrate;
• a bit line extending along a first direction, the bit line crossing over first and second source/drain regions in the substrate for the transistor, and making electrical contact with said first source/drain region;
• a word line extending along a second direction perpendicular to the first direction, the word line providing a gate electrode for the memory cell transistor;
• a first insulation layer on top of the substrate having a portion covering the top of the word line;
• a plate line extending parallel to the word line, but separated therefrom by the first insulation layer, the plate line constituting a bottom capacitor electrode in each memory cell through which it passes;
• a ferroelectric dielectric line parallel to and on top of the plate line;
• the plate line and the ferroelectric dielectric line being centrally located above the word line;
• wherein, with reference to said first direction, said plate line is as wide as said ferroelectric dielectric line;
• wherein no side of said ferroelectric dielectric line in the memory cell extends beyond a side of the bottom electrode;
• a second insulation layer having a portion located on top of the first insulation layer, and having another portion covering sides of the plate line and the ferroelectric dielectric line;
• a top electrode contacting an upper surface of the ferroelectric line;
• a local interconnect for the memory cell, the local interconnect being self-aligned to and extending laterally from a lateral edge of the top electrode along the first direction and downward to make electrical contact with said second source/drain region via a first contact window etched through the first and second insulation layers, the local interconnect being in full contact with and completely covering the top surface of the top electrode, the local interconnect and first contact window being situated beneath the bit line;
• the plate line, ferroelectric dielectric line, and the top electrode forming a ferroelectric capacitor substantially at the intersection of the bit line and the word line;
• wherein the bit line extends over the ferroelectric capacitor;
• a third insulation layer having a portion located on top of said second insulation layer having another portion located on top of said local interconnect;
• wherein said bit line extends through a second etched contact window located over first source/drain region to make said electrical contact therewith;
• said second etched contact window extending through said first, second, and third insulation layers;
• wherein the plate line, ferroelectric line, bit line, and word line extend to a plurality of other memory cells.