Method to solve holes in passivation by metal layout

The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising:

• providing an insulating layer over semiconductor device structures in and on a semiconductor substrate;
• forming metal lines having a metal line layout wherein said metal lines have a fixed spacing throughout the length of said metal lines and wherein said metal lines have a larger width around a turn than they have throughout the remainder of their length;
• depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer between said metal lines and wherein said metal layout prevents openings from being made within said passivation layer to said tunnels;
• covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels;
• patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer;
• and
• removing said resist layer to complete said fabrication of said integrated circuit.

The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising:

• providing an insulating layer over semiconductor device structures in and on a semiconductor substrate;
• forming metal lines having a metal line layout wherein said metal lines have a fixed spacing throughout the length of said metal lines and wherein said metal lines have a larger width around a turn than they have throughout the remainder of their length and wherein metal islands are formed perpendicular to said metal lines at the terminals of said metal lines;
• depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer between said metal lines and at the terminals of said metal lines and wherein said metal layout prevents openings from being made within said passivation layer to said tunnels;
• covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels;
• patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer;
• and
• removing said resist layer to complete said fabrication of said integrated circuit.

The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising:

• providing an insulating layer over semiconductor device structures in and on a semiconductor substrate;
• opening dummy vias in said insulating layer at the terminals of planned metal lines;
• forming metal lines overlying said insulating layer wherein said terminals of said metal lines fill said dummy vias thereby reducing the aspect ratio of the spacing of said metal lines;
• depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer at the terminals of said metal lines and wherein said reduced aspect ratio prevents openings from being made within said passivation layer to said tunnels;
• covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels;
• patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer;
• and
• removing said resist layer to complete said fabrication of said integrated circuit.