High capacity semiconductor dopant deposition/oxidization process using a single furnace cycle
AssigneeSony Electronics Inc.
InventorJon A. Gwin
Life of this patent
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Abstract
A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.
Claims20
A method for processing semiconductor wafers in a single cycle of a temperature chamber without removal of the wafers, comprising the ordered steps of:
- heating said chamber to a chamber temperature lower than which would produce diffusion of a dopant in said wafer;
- maintaining said chamber temperature while forming a layer of dopant glass on a surface of said wafers;
- increasing said chamber temperature to a diffusion temperature to drive said dopant into said wafers in an inert environment;
- maintaining said diffusion temperature and inert environment for a period of time to drive said dopant into said wafers;
- elevating said chamber temperature to an oxidizing temperature and generating said oxidizing environment for a period of time to achieve oxidation of said wafer.
The method for processing semiconductor wafers in a quartz temperature chamber using a single furnace cycle, comprising the ordered steps of:
- heating said chamber to a chamber temperature of approximately 850.degree. C.;
- inserting a load of a plurality 125 mm silicon wafers into a center of said chamber;
- stabilizing said chamber temperature in a gas mixture of 2050 sccm of N.sub.2 and 3500 sccm of O.sub.2 ;
- maintaining said chamber temperature and gas mixture while forming a layer of a dopant glass on said wafers by introducing POCl.sub.3 vapor for 75 minutes, wherein said POCl.sub.3 vapor is generated by passing said N.sub.2 gas through a bubbler containing liquid POCl.sub.3 with said liquid POCl.sub.3 held at a temperature below ambient temperature;
- increasing said chamber temperature to a diffusion temperature of 945.degree. C. to diffuse said dopant into said wafers in a nitrogen environment produced by a flow of 6000 sccm of N.sub.2 ;
- maintaining said diffusion temperature and nitrogen environment for 50 minutes to drive said dopant into said wafers;
- elevating said chamber temperature to an oxidizing temperature of 980.degree. C. in an inert ambient;
- generating an oxygen and hydrogen environment by establishing a flow of 5000 sccm of H.sub.2 and 3000 sccm of O.sub.2 within said chamber;
- oxidizing said wafers by maintaining said oxidizing temperature and hydrogen and oxygen environment for a period of time to achieve oxidization of said wafers;
- reducing said chamber temperature to 800.degree. C.;
- removing said wafers from said chamber;
- and
- introducing an oxygen flow of about 1000 sccm of O.sub.2 at a chamber temperature of 800.degree. C. into said chamber for at least about 45 minutes to react with any remaining dopant inside said chamber.
A method for processing semiconductor wafers in a temperature chamber using a single furnace cycle, comprising the ordered step of:
- establishing a target silicon resistance for said wafers;
- heating said chamber to a chamber temperature;
- maintaining said chamber temperature while forming a layer of dopant glass on a surface of said wafers;
- said chamber temperature being too low to cause diffusion of said dopant in said wafer to a degree which would produce a silicon resistance which is less than said target said target resistance;
- increasing said chamber temperature to a diffusion temperature to drive said dopant into said wafers in an inert environment;
- maintaining said diffusion temperature and inert environment for a period of time to drive said dopant into said wafers to produce said target silicon resistance;
- elevating said chamber temperature to an oxidizing temperature to achieve oxidation of said wafer in an oxidizing environment;
- and
- oxidizing said wafer by maintaining said oxidizing temperature and generating said oxidizing environment for pre-established period to time to achieve a target level of oxidization.
A method for processing semiconductor wafers in a quartz temperature chamber, comprising the ordered steps of;
- heating said chamber to a chamber temperature of 850.degree. C.;
- inserting a load of silicon wafers into a center of said chamber;
- stabilizing said chamber temperature in an gas mixture of 2050 sccm of N.sub.2 and 3500 sccm of O.sub.2 ;
- maintaining said chamber temperature and gas mixture while forming a layer of a dopant glass on said wafers by introducing POCl.sub.3 vapor for 75 minutes, wherein said POCl.sub.3 vapor is generated by passing said N.sub.2 gas through a bubbler containing liquid POCl.sub.3 with said liquid POCl.sub.3 held at a temperature below ambient temperature;
- increasing said chamber temperature to a diffusion temperature of 900.degree. to 1100.degree. C. to diffuse said dopant into said wafers in a nitrogen environment produced by a flow of 6000 sccm of N.sub.2 ;
- maintaining said diffusion temperature and nitrogen environment for 50 minutes to diffuse said dopant into said wafers;
- generating an oxygen and hydrogen environment by establishing a flow of 5000 sccm of H.sub.2 and 3000 sccm of O.sub.2 within said chamber;
- oxidizing said wafer by maintaining said diffusion temperature and hydrogen and oxygen environment for a period of time to achieve oxidization of said wafers;
- reducing said chamber temperature to 800.degree. C.;
- removing said wafers from said chamber;
- and
- introducing an oxygen flow of 10000 sccm of O.sub.2 at a chamber temperature of 800.degree. C. into said chamber for at least 45 minutes to react with any remaining dopant inside said chamber.
Dependencies are inferred from the claim text.