Back to results
US 5,494,843 AGranted
Method for forming MOSFET devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJenn-Ming Huang
Life of this patent
Estimating the term…
Abstract
A method for fabricating CMOS chips, using a SRAM cell composed of, both NFET and PFET devices, or only NFETs, as well as incorporating NFET and PFET peripheral devices, is described. This process features an NFET, used in the SRAM cell, where a lightly doped arsenic source and drain region is used to achieve maximum device performance, in terms of saturation current, as well as gate to diffusion overlap capacitance. However the NFET used for the peripheral device is fabricated using a lightly doped phosphorous source and drain region, to allow for more protection against the deleterious hot carrier injection phenomena.
Claims30
A method for forming MOSFET devices on semiconductor substrates, comprising the steps of:
- growing a screen oxide on said semiconductor substrate;
- ion implanting a first conductivity imparting dopant into a first specific area of said semiconductor substrate;
- ion implanting a second conductivity imparting dopant into a second specific area of said semiconductor substrate;
- forming field oxide regions in said semiconductor substrate, for isolation of device regions;
- ion implantation of a third conductivity imparting dopant into said semiconductor substrate, not covered by said field oxide regions;
- removal of said screen oxide from said semiconductor substrate, not covered by said field oxide regions;
- growing a gate oxide on surface of said semiconductor substrate, not covered by said field oxide regions;
- depositing a polysilicon layer on said gate oxide, and on said field oxide regions;
- ion implanting a fourth conductivity imparting dopant into said polysilicon layer;
- patterning of said polysilicon layer to form polysilicon gate structures on said gate oxide;
- ion implanting a fifth conductivity imparting dopant into said device region, in an area of said second specific region of said semiconductor substrate, not covered by said polysilicon gate structure;
- annealing of said semiconductor substrate;
- ion implanting a sixth conductivity imparting dopant into said device region, in a different area of said second specific region of said semiconductor substrate, not covered by said polysilicon gate structure;
- ion implanting a seventh conductivity imparting dopant into said device region, in said first specific region of said semiconductor substrate, not covered by polysilicon gate structure;
- depositing a first insulator layer on surface of said semiconductor substrate;
- anisotropic etching to remove said first insulator layer to form insulator spacer on sidewalls of said polysilicon gate structure;
- ion implanting an eighth conductivity imparting dopant into said device region, in said second specific region of said semiconductor substrate, not covered by said polysilicon gate structure;
- and
- ion implanting a ninth conductivity imparting dopant into said device region, in said first specific region of said semiconductor substrate, not covered by said polysilicon gate structure.
16 more elements
A method for fabricating a CMOS chip on a semiconductor substrate, consisting of stactic random access memory, (SRAM), cells, with both P type and N type MOSFET devices, and peripheral N type MOSFET devices, comprising the steps of:
- growing a screen oxide on said semiconductor substrate;
- ion implanting a first conductuctivity imparting dopant into a first specific region of said semiconductor substrate, to form an N well region;
- ion implanting a second conductivity imparting dopant into a second specific region of said semiconductor substrate, to form a P well region;
- forming field oxide regions in said semiconductor substrate, for isolation of device region;
- ion implantation of a third conductivity imparting dopant into said semiconductor substrate, not covered by said field oxide regions;
- removal of said screen oxide from said semiconductor substrate, not covered by said field oxide regions;
- growing a gate oxide on surface of said semiconductor substrate, not covered by said field oxide regions;
- depositing a polysilicon layer on said gate oxide and on said field oxide regions;
- ion implanting a fourth conductivity imparting dopant into said polysilicon layer;
- patterning of said polysilicon layer to form polysilicon gate structures on said gate oxide;
- ion implanting a fifth conductivity imparting dopant into said device region, in a specific area of said P well region to be used for said SRAM cell, to form N type lightly doped source and drain regions;
- annealing of said semiconductor substrate;
- ion implanting a sixth conductivity imparting dopant into said device region, in another specific area of said P well region to be used for said peripheral N type MOSFET devices, to form N type lightly doped source and drain region;
- ion implanting a seventh conductivity imparting dopant into said device region, in a specific area of N well region, to form P type lightly doped source and drain region;
- depositing a first insulator layer on surface of said semiconductor substrate;
- anisotropic etching to remove said first insulator layer to form insulator spacer on sidewalls of said polysilicon gate structure;
- ion implanting an eighth conductivity imparting dopant into said device region, in said specific area of said P well region to be used for said SRAM cell, and in another said specific area of said P well region, to be used for said peripheral N type MOSFET devices, to form heavily doped, N type source and drain region;
- and
- ion implanting a ninth conductivity imparting dopant into said device region, in said specific area of N well region, to form heavily doped P type source and drain region.
16 more elements
Dependencies are inferred from the claim text.