Dual photo-resist process for fabricating high density DRAM
AssigneeUnited Microelectronics Corp.
InventorsGary Hong, Chen-Chiu Hsue
Life of this patent
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Abstract
A dual photo-resist process for fabricating capacitor plates of a DRAM is disclosed including the step of forming a capacitor on a semiconductor IC surface. A first plurality of photo-resist regions which are separated from each other by spaces are then formed on the capacitor plate layer. At least one second photo-resist region is then formed on the capacitor plate layer which partially fills a space between, and is adjacent to one of, two of the first photo-resist regions. The capacitor plate layer is then etched below the spaces between the first and second photo-resist regions to form a plurality of individual capacitor plates including one capacitor plate for each DRAM cell.
Claims8
A process for fabricating a DRAM cell capacitor comprising the steps of:
- forming a capacitor plate layer on a semiconductor surface;
- using a first mask, forming a first photo-resist layer on the capacitor plate layer;
- patterning the first photo-resist layer to define a plurality of first photo-resist regions on said capacitor plate layer, the photo-resist regions being separated from each other by spaces which expose the capacitor layer;
- after patterning the first photo-resist layer, forming a second photo-resist layer on the capacitor plate layer;
- shifting the mask in a direction parallel to a surface of the capacitor plate layer and toward a center of the spaces;
- using the shifted mask, patterning the second photo-resist layer to define a plurality of second photo-resist regions which partially fill said spaces;
- and
- etching said capacitor plate layer at said spaces to form a capacitor plate region.
A process for fabricating a DRAM comprising the steps of:
- forming a plurality of MOSFETs each having a drain;
- forming an insulating layer on said MOSFETs;
- forming a plurality of vias in said insulating layer, each via connecting the drain of one of the plurality of MOSFETs and a surface of said insulating layer;
- forming a capacitor plate layer on said insulating layer surface, said capacitor plate layer being connected to each of said vias;
- forming a first photo,resist layer on the capacitor plate layer;
- using a mask, patterning the first photo-resist layer to define a first plurality of photo-resist regions on said capacitor plate layer which regions are separated from each other by spaces which expose the capacitor plate layer;
- forming a second photo-resist layer on the capacitor plate layer;
- shifting the mask in a direction parallel to a surface of the capacitor plate layer and toward a center of the spaces;
- patterning the second photo-resist layer to define second photo-resist regions which partially fill said spaces;
- and
- after the step of patterning the second photo-resist layer, etching said capacitor plate layer exposed by said spaces to form a plurality of individual capacitor plate regions.
Dependencies are inferred from the claim text.