US 5,493,723 AGranted

Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits

AssigneeNational Semiconductor Corporation

InventorsMotti Beck, Ran Talmudi, Sorin Iacobovici

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Abstract

A processor emulation system for testing processor operation. First and second identical microprocessors are used together with a target system which includes the main memory. One microprocessor performs an in-system emulation (ISE) function by operating in lock step with the second processor which functions as the master processor. A mode control signal is used to switch the microprocessors between a normal operating mode and an ISE mode. Normal microprocessor signals are outputted on predetermined terminals for the processor in the normal operating mode and the parallel contents of the processor program counter are outputted on the same predetermined terminals when the microprocessor is in the ISE mode. The master processor provides output signals to the target system, with the ISE processor and the master processor both receiving signals from the target system. Operation of the master processor can be ascertained by monitoring the program counter output of the ISE processor.

Claims10

Dependent claims

A processor emulation system for testing processor operation, said system comprising:

first and second processors, each of the processors including a program counter which contains a program counter value comprising a plurality of program counter bits which represent an instruction address which corresponds to a processor instruction currently being executed by the processors, with each of said processors further including
(a) a multiplicity of processor terminals which function to provide an interface for signals exchanged between the processor and an environment external to the processor, with the processor terminals including a first group of terminals to exclusively output signals from the processor, a second group of terminals which function exclusively to input signals to the processor and a third group of terminals which function to both input signals to the processor and output signals from the processor;
(b) select means for selectively parallel coupling either a first group of processor signals to predetermined ones of the first group of processor terminals or a second group of processor signals to the same predetermined ones of the first group of processor terminals in response to a mode control signal, with the second group of processor signals representing at least a majority of the program counter bits;
wherein the mode control signal can be used to produce the at least a majority of program counter bits at the same predetermined ones of the first group of processor terminals when the processor operating in an in-system emulation mode and can also be used to produce the first group of processor signals at the same predetermined ones of the first group of processor terminals when the processor operating in a normal operation mode;
and
said processor emulation system further including
a target system which includes at least one input/output device and, said target system receives target system input signals from one of the first and second processors and produces target system output signals;
wherein the first processor is provided with said mode control signal such that the first processor is operating in the in-system emulation mode and the second processor is provided with the mode control signal such that the second processor is operating in the normal operating mode and wherein the output signals of the target system are coupled to terminals included in the second group of terminals of the first and second processors whereby operation of the second processor can be monitored by way of the majority of program counter bits provided at the first group of processor terminals of the first processor.

5 more elements

A method of testing processor operations utilizing first and second processors and a target system with the first and second processors each including a program counter which contains a program counter value comprising a plurality of program counter bits which represent an instruction address which corresponds to a processor instruction currently being executed by the processors and a multiplicity of processor terminals which function to provide an interface for signals exchanged between the processor and an environment external to the processor, with the processor terminals including a first group of terminals which function to exclusively output signals from the processor, a second group of terminals which function exclusively to input signals to the processor and a third group of terminals which function to both input signals to the processor and output signals from the processor, wherein the processors include a first group of processor signals and a second group of processor signals, the second group of processor signals representing at least a majority of the program counter bits, and wherein the processors each include select means for selectively coupling either the first group of processor signals to predetermined ones of the first group of processor terminals or the second group of processor signals to the same predetermined ones of the first group of processor terminals and the target system including at least one input/output device and said target system receives target system input signals from one of the first and second processors and produces target system output signals, the method comprising the following steps:

generating a mode control signal for switching the processors between a normal operating mode and an in-system emulation mode;
placing the first processor in said in-system emulation mode by coupling the second group of processor signals of the first processor to the first group of terminals of the first processor;
placing the second processor in the normal operating mode by coupling the first group of processor signals of the second processor to the first group of terminals of the second processor:
and
coupling the output signals of the target system to terminals included in the second group of processor terminals of the first and second processors;
whereby operation of the second processor can be evaluated by monitoring the program counter bits produced at the first group of processor terminals of the first processor.

3 more elements

Dependencies are inferred from the claim text.