US 5,493,687 A · RISC microprocessor architecture implementing multiple typed register sets

Abstract

A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

Claims5

Dependent claims

In a data processing system, which includes a central processing unit (CPU) which performs operations according to an instruction, the operations operating upon integer data, a data register system comprising:

a first register set including a plurality of first registers each for holding the integer data;
a second register set including a plurality of second registers each for holding the integer data and for holding floating point data, wherein the instruction includes a field specifying which of the first and second register sets is to be accessed in response to the instruction;
means, responsive to the field, for accessing the first register set or the second register set as specified by the field, including
i) reading means for reading an operand value from either the first register set or second register set as specified by the field, and
ii) writing mean for writing a result value to the first register set or the second register set as specified by the field.

2 more elements

An apparatus comprising:

execution means for executing instructions, the instructions performing operations upon operands to generate results, each instruction specifying a respective source address for each operand and a destination address for the result of the instruction, each address specifying a register set and an offset;
a first register set including a plurality of individually addressable registers each for storing integer values;
first access means for writing and reading values to and from the first register set according to a given instruction, the first access means including,
i) first reading means, responsive to the given instruction having a given source address which specifies the first register set as a source for an operand of the given instruction, for reading the operand's value from the first register set at the offset specified by the given source address, and
ii) first writing means, responsive to the given instruction having a given destination address which specifies the first register set as a destination for the result of the given instruction, for writing the result's value to the first register set at the offset specified by the given destination address;
a second register set including a plurality of individually addressable registers, wherein each addressable register is configured to store floating point values and integer values;
and
second access means for writing and reading integer and floating point values to and from the second register set according to the given instruction, the second access means including,
i) second reading means, responsive to the given instruction having a given source address which specifies the second register set as a source for an operand of the given instruction, for reading the operand's value from the second register set at the offset specified by the given source address, and
ii) second writing means, responsive to the given instruction having a given destination address which specifies the second register set as a destination for the result of the given instruction, for writing the result's value to the second register set at the offset specified by the given destination address.

7 more elements

Dependencies are inferred from the claim text.

RISC microprocessor architecture implementing multiple typed register sets

Life of this patent

RISC microprocessor architecture implementing multiple typed register sets

Life of this patent

Abstract

Claims5