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AssigneeAdvanced Micro Devices, Inc.
InventorsDouglas D. Gephardt, James R. MacDonald, Rita M. O'Brien
Estimating the term…
An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor such as activities of a floating-point coprocessing subunit. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an external power management unit. Power management decisions are made by an external power management unit. The power management unit receives the encoded messages on the power management message bus and responsively makes decisions as to the appropriate power management mode to enter. The power management unit includes a clock control unit coupled to an internal clock generator of the integrated processor for controlling the frequencies of a CPU clock signal and a system clock signal. The power management unit further includes a power control unit for controlling the application of power to various external peripheral devices.
A computer system comprising:
A method for managing power within a computer system, wherein said computer system includes an integrated processor having a CPU core and at least one on-chip peripheral device, said method comprising the steps of:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
No related US applications are recorded in the indexed filing history.
Power saving characterised by the action undertaken: by lowering clock frequency
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
Power saving characterised by the action undertaken: power saving in peripheral device
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
Term ended 6 Apr 2014 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates to computer systems and more particularly to power management architectures employed within computer systems.
2. Description of the Relevant Art
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
FIG. 1 is a block diagram of a computer system employing a power management architecture in accordance with the present invention.
FIG. 2 is a block diagram that illustrates details associated with one implementation of a power management architecture according to the present invention.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Referring now to the drawings, FIG. 1 is a block diagram of a computer system 100 including an integrated processor 102 coupled to a power management unit 104. Integrated processor 102 includes a CPU core 104 coupled to a clock generator 106 and to a memory controller 108. Integrated processor 102 further includes a meesage unit 112 and a plurality of on-chip peripherals represented generally by block 110.
Generally speaking, power management unit 104 is provided for managing the power within computer system 100, and is contained on an integrated circuit that is separate from integrated processor 102. Power management unit 104 receives power management (PM) messages from message unit 112 indicative of the operation of integrated processor 102. Using these messages, power management unit 104 generates a set of clock control signals to control the generation of a CPU clock signal and a system clock signal by clock generator 106. Specifically, the clock control signals are capable of causing the CPU and system clock signals to be either slowed or stopped. Power management unit 104 further generates a set of peripheral power control signals that control the application of power to various external peripheral devices. Further details regarding a computer system that conforms to the block diagram of FIG. 1 are provided below.