Register for identifying processor characteristics

A computer system comprising a main processor and a coprocessor coupled to said main processor comprising:

• a. an identification register in said coprocessor comprising a contents including a flag for identifying whether the coprocessor comprises static logic components;
• b. a clock coupled to said coprocessor;
• c. a bus logic control unit in said coprocessor coupled to said main processor for transferring the contents of said identification register to said main processor upon the receipt of a first instruction code sent by said main processor;
• d. a bus logic control unit in said main processor coupled to said coprocessor for receiving the contents of said identification register;
• e. a register in said main processor coupled to said bus control logic unit in said main processor for storing the contents of the identification register received from said coprocessor;
• f. a logic unit in the main processor coupled to said register for determining the contents of the register in the main processor responsive to said storing of the contents of the identification register received from the coprocessor;
• and
• g. a clock halt circuit coupled to said clock and said logic unit for stopping the clock operative upon said determining by said logic unit that said coprocessor comprises static logic devices.

A processor comprising:

• a. an identification register in said processor comprising a contents including a flag for internally identifying whether said processor comprises static logic components;
• b. a plurality of pins coupled to said identification register for interfacing said processor with a second device including a first pin, an active state on said first pin externally indicating that said processor is comprised of static logic devices and an inactive state on said first pin externally indicating that said processor is not comprised of said static logic devices;
• and
• c. a control unit in said processor coupled to said first pin, said control unit having an activation circuit coupled to said first pin for activating said first pin upon the receipt of a first instruction code sent by said second device and when said flag has a predetermined state indicating that said processor is comprised of said static logic devices.

A computer system comprising a first processor and a second processor coupled to said first processor further comprising:

• a. an identification register in said second processor comprising a contents including a flag for identifying whether the second processor comprises static logic components;
• b. a clock coupled to said second processor;
• c. a bus logic control unit in said second processor coupled to said first processor and said identification register for transferring the contents of said identification register to said first processor;
• d. a bus logic control unit in said first processor coupled to said second processor for receiving the contents of said identification register;
• e. a register in said first processor coupled to said bus logic control unit in said second processor for storing the contents of the identification register received from said second processor;
• f. a logic unit in the first processor coupled to said register for determining the contents of the register in the first processor responsive to said storing of the contents of the identification register received from the second processor;
• and
• g. a clock halt circuit coupled to said clock and said logic unit for stopping the clock operative upon the determining by said logic unit that the second processor comprises static logic devices.