Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution

A method for providing a system level simulation of a system having an input/output subsystem and a host system, said simulation of said system being capable of implementing a two-way communication between simulation of said input/output subsystem and said host system, and resolving potential deadlock situations comprising the steps of:

• simulating an input/output subsystem using a logic level simulator, said simulated input/output subsystem being capable of a direct memory access;
• concurrently simulating a host system with said simulating of said input/output subsystem, said simulating said host system being performed using an instruction level simulator with signals transmitted between said simulated input/output subsystem and said simulated host system, said simulated host system being capable of both processor read/write access and direct memory access;
• and
• resolving deadlocks between said simulated input/output subsystem and said simulated host system, said deadlock may occur during said two-way communication between said simulated host system and said simulated input/output subsystem when said simulated input/output subsystem performs a direct memory access at the same time as when said simulated host system performs a processor read/write access, causing said simulated input/output subsystem and said simulated host system to wait for data and an acknowledgment from each other at the same time, said resolving being performed by deferring said processor read/write access, an said two-way communication occurring through a simulated interprocess communication.