US 5,493,669 AGranted

Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits

AssigneeMotorola, Inc.

InventorMarvin A. Denman, Jr.

Life of this patent

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Abstract

A data processor has a plurality of execution units (12), a rename buffer (14) coupled to at least one of the execution units and a plurality of architectural registers (16) coupled to at least one execution unit and to the rename buffer. The rename buffer periodically receives and stores the result and periodically receives requests for the operand. Each received result and operand is associated with an architectural register. The rename buffer periodically forwards one of a set of received results to an execution unit. Each received result of the set is associated with the same architectural register. The rename buffer is operable to determine which entry is the most recently allocated among several that will update the same architectural register. This ability to both manage results destined for the same architectural register and to forward only the appropriate value increases data processor throughput and reduces instruction stalls.

Claims2

Dependent claims

A data processor comprising:

a plurality of execution units, the execution units operable to perform a plurality of instructions received from a memory system, at least one of the plurality of instructions requiring an operand, at least one of the plurality of instructions generating a result;
a plurality of architectural registers coupled to at least one of the execution units, the plurality of architectural registers supplying operands to the at least one of the plurality of execution units, the plurality of architectural registers periodically receiving the result of the at least one instruction generating a result;
a plurality of memory means, each memory means storing a result, a tag representative of the architectural register associated with the result and a first-most-recently-allocated bit and a second-most-recently-allocated bit each associated with the result;
allocation means coupled to at least one of the execution units and to the plurality of memory means, the allocation means periodically receiving a first tag identifying an architectural register, storing the first tag in a predetermined one of the memory means, setting the first-most-recently-allocated bit associated with the predetermined one of memory means to a first logic state, setting each first-most-recently-allocated bit of a subset of the memory elements to a second logic state, the subset of memory elements comprising a tag logically equivalent to the first tag, and storing each first-most-recently-allocated bit in an associated second-most-recently-allocated bit location responsive to a speculative branch;
forwarding means coupled to at least one of the execution units and to the plurality of memory means, the forwarding means receiving a request for an operand, the request comprising the first tag, the forwarding means comparing the first tag to each tag stored in the plurality of memory means, and forwarding a selected result to an execution unit responsive to the step of comparing, the selected result associated with a selected one of the plurality of memory means, the selected one of the plurality of memory means comprising a tag and a first-most-recently-allocated bit corresponding in logic state to the first one of the architectural registers and to the first logic state of the first-most-recently-allocated bit, respectively;
and
tag means coupled to the forwarding means to forward an address of the one of the plurality of memory means associated with the selected result.

4 more elements

A method of operating a data processor comprising the steps of:

at a first time, storing a first tag and a first first-most-recently-allocated bit in a tag field and in a first-most-recently-allocated-bit-field, respectively, of a first one of a plurality of sets, each one of the plurality of sets comprising a tag field, a first-most-recently-allocated-bit-field, and a second-most-recently-allocated-bit-field, the first tag identifying an address of a first memory cell associated with a first result, the first result being an output of a first instruction executed by an execution unit of the data processor, the first first-most-recently-allocated bit associated with the first result, the first first-most-recently-allocated bit assuming a first logic state;
at a second time subsequent to the first time, storing a second tag and a second first-most-recently-allocated bit in a second one of the plurality of sets, the second tag identifying an address of a memory cell associated with a second result and the second first-most-recently-allocated bit associated with the second result, the second result being an output of a second instruction executed by the execution unit, the second first-most-recently-allocated bit assuming the first logic state, and storing a second logic state in the first-most-recently-allocated bit field of a subset of the plurality of sets, each of the contents of the tag fields of the subset of the plurality of sets logically equivalent to the second tag:
at a third time, receiving a requested tag of a requested result, comparing the requested tag and the first logic state to the tag field and to the first-most-recently-allocated bit field, respectively, of each of the plurality of sets, forwarding a result associated with a selected set, the contents of the tag field and the contents of the first-most-recently-allocated-bit-field of the selected set logically equivalent to the requested tag and the first logic state;
at a fourth time subsequent to the first time, receiving the first result from a communication bus within the data processor and storing the first result in the first memory cell;
and
at a fifth time subsequent to the first time, issuing a speculative branch instruction to the execution unit and storing the contents of each first-most-recently-allocated bit field in an associated second-most-recently-allocated bit field.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/025,453Filed 3 Mar 1993
Granted: 20 Feb 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/3863
Recovery, e.g. branch miss-prediction, exception handling: using multiple copies of the architectural state, e.g. shadow registers
G06F 9/38
Arrangements for executing machine instructions, e.g. instruction decode: concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding